© Copyright 2003 Nassda Corporation OpenAccess 2.0 — A Nassda Perspective Graham Bell, Director of Marketing

©Nassda Corporation Nanometer Verification Flow  File based flow in dotted arrows  Direct API and shared in-memory data flow in solid arrows  Nassda will partner with customers and vendors for a full- chip nanometer verification flow  File based flow in dotted arrows  Direct API and shared in-memory data flow in solid arrows  Nassda will partner with customers and vendors for a full- chip nanometer verification flow OpenAccess DB Schematic Editor Layout Editor DRC / LVS Layout Parasitic Extraction Transistor Netlist Pre-layout & Post-layout Simulation & Analysis Waveforms, Analysis and Reports DSPF / SPEF

©Nassda Corporation Parasitic Detailed Model View  Resistor  Gnd Capacitor  Coupling Capacitor  Inductor  Mutual Inductor  Resistive Inductor  Diode  Resistor  Gnd Capacitor  Coupling Capacitor  Inductor  Mutual Inductor  Resistive Inductor  Diode

©Nassda Corporation Detailed Parasitic Modeling in OA 2.0  Fast creation of objects 1.5 million parasitics per minute  Fast parasitic search 2 seconds to build search table for 1 million parasitics Immediate search  Efficient database file size 1 Million objects < 30Mb  Fast creation of objects 1.5 million parasitics per minute  Fast parasitic search 2 seconds to build search table for 1 million parasitics Immediate search  Efficient database file size 1 Million objects < 30Mb

©Nassda Corporation Detailed Parasitic Processing Results

©Nassda Corporation Next Steps  Live databases from customers  Pre- and post-layout netlist  Browsing and debug capabilities  Partnering with others to demonstrate a nanometer verification flow  Future: post-layout design optimization  Live databases from customers  Pre- and post-layout netlist  Browsing and debug capabilities  Partnering with others to demonstrate a nanometer verification flow  Future: post-layout design optimization