Heterogeneous FPGA architecture and CAD Peter Jamieson Supervisor: Jonathan Rose.

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Presentation transcript:

Heterogeneous FPGA architecture and CAD Peter Jamieson Supervisor: Jonathan Rose

Motivation FPGAs are a popular technology for implementing digital circuits Consist of programmable logic and routing Fabric

Modern FPGA Add hard circuit structures to improve speed, area efficiency, and power consumption –Flip-flop –Memory –Multiplier

High-level Goals of our Research To improve the speed, area, and power consumption of an FPGA by architecting a better specific circuit To understand and develop algorithms needed to synthesize designs to these types of FPGAs

Past Research Odin – Front-end Verilog Synthesis Tool for Heterogeneous FPGAs Used flow to implement Multiplexer to Multiplier mapping

Latest Research What if hard structures are not used? Wasted silicon and routing resources (70- 90% of FPGA area from routing)!!! Looking into architecting new heterogeneous FPGA tiles to improve area efficiency