數位系統實驗 Experiment on Digital System Lab06: Verilog HDL and FPGA (2) 負責助教：葉俊顯 stanley

2015/10/202 Outline Introduction to VeriLite Programming VeriLite Verification using VeriInstrument Lab

2015/10/203 Outline Introduction to VeriLite Programming VeriLite Verification using VeriInstrument Lab

2015/10/204 Introduction to VeriLite JTAG 電源線 Reset USB 開關

2015/10/205 Introduction to VeriLite

2015/10/206 Introduction to VeriLite 虛擬元件 利用 USB 溝通

2015/10/207 Outline Introduction to VeriLite Programming VeriLite Verification using VeriInstrument Lab

2015/10/208 Programming VeriLite 一般組合電路不會有 clk 訊號出現， clk 只會 在循序電路出現 備註：此 FPGA 板子需要額外的 clk 訊號 腳位設定才可以動作，所以務必記得加入

2015/10/209 Programming VeriLite Start compilation

2015/10/2010 Programming VeriLite Open Assignment editor

2015/10/2011 Programming VeriLite Show input and output pins

2015/10/2012 Programming VeriLite Pin assignment Double click

2015/10/2013 Programming VeriLite Assign pin location to all inputs and outputs and add Clk  Please refer to pin.xls for pin location assignment  Clock must be assigned to location Pin_28

2015/10/2014 Programming VeriLite Start compilation

2015/10/2015 Programming VeriLite Programming device

2015/10/2016 Programming VeriLite Hardware setup: add USB-Blaster

2015/10/2017 Programming VeriLite Programming device

2015/10/2018 Outline Introduction to VeriLite Programming VeriLite Verification using VeriInstrument Lab

2015/10/2019 Verification using VeriInstrument 一定要先確認 !!!

2015/10/2020 Verification using VeriInstrument Specify the name of project file and the pin information file (*.qsf) generated by QuartusII

2015/10/2021 Verification using VeriInstrument Check pin assignment

2015/10/2022 Verification using VeriInstrument Add I/O device

2015/10/2023 Verification using VeriInstrument Add I/O device Drag here

2015/10/2024 Verification using VeriInstrument Assign user pins Drag here

2015/10/2025 Verification using VeriInstrument Run FPGA

2015/10/2026 Outline Introduction to VeriLite Programming VeriLite Verification using VeriInstrument Lab

2-Bit by 2-Bit Binary Multiplier Four input, B1,B0, A1,A0 Four output, C3, C2, C1, C0

Lab

Hint xor xor01(s, x, y); and and01(c, x, y); assign s=x^y; assign c=x&y; reg s,c; or y) begin s=x^y; c=x&y; end

Notice 請勿在桌面建立 Project 及請勿命名中文資料夾 Device family 請確認與 FPGA Chip 符合 (EP1C6Q240C8) Top module name & Project name 需要一致 確認 module … endmodule 為 keyword 變成藍色字體 30