Finite State Machines VHDL ET062G & ET063G Lecture 6 Najeem Lawal 2012

FINITE STATE MACHINES OUTLINE –Range Sensor display –FSM in VHDL Medvedev FSM Moore FSM Mealy FSM –FSMD – FSM and Data path

RANGE SENSOR DISPLAY Najeem Lawal, VHDL ET062G & ET063G Lecture 6 1.Specify the number of rows 2.Specify the location of the display 3.Determine the effective number of bits for range sensor data

RANGE SENSOR DISPLAY Najeem Lawal, VHDL ET062G & ET063G Lecture 6 1.Specify the number of rows 2.Specify the location of the display 3.Determine the effective number of bits for range sensor data What do you need 1.2 counters 1.Column counter to assess the content of the memory 2.Row counter to know what to display 2.Comparator

RANGE SENSOR DISPLAY Najeem Lawal, VHDL ET062G & ET063G Lecture 6 1.Specify the number of rows 2.Specify the location of the display 3.Determine the effective number of bits for range sensor data if (vcount > 300 and vcount < 365) then if ((vcount - 300) >= (64 - pixel_data(7 downto 2))) then red_out <= "111"; green_out<= "111"; blue_out <= "11"; else red_out <= "000"; green_out<= "000"; blue_out <= "00"; end if; else red_out <= red_in; green_out <= green_in; blue_out <= blue_in; end if;

RANGE SENSOR DISPLAY Najeem Lawal, VHDL ET062G & ET063G Lecture 6 1.Specify the number of rows 2.Specify the location of the display 3.Determine the effective number of bits for range sensor data To solve this problem 1.use if statements 2.use case statements 3.or combine into FSM

USE CASES Najeem Lawal, VHDL ET062G & ET063G Lecture 5 STUDENT PROJECT PRESENTATIONS –Farid –Ashkan –Patrick HOW THE SOLVED –Range sensor –Edge detection –Sliding window

DESIGN OF STATE MACHINES Najeem Lawal, VHDL ET062G & ET063G Lecture 6 MANUAL DESIGN WORK FLOW: Develop a state graph that captures the problem Develop a solution state graph Coding of states Select register elements (D-,T-,JK- ?) Develop a transition table Develop boolean functions for and  Design circuitry at gate level

DESIGN OF STATE MACHINES Najeem Lawal, VHDL ET062G & ET063G Lecture 6 AUTOMATIC SYNTHESIS Develop a state diagram for the problem Write VHDL-code that captures the problem Automatic synthesis will perform coding of state graph and generate a gate level netlist

FINITE STATE MACHINES AND VHDL COMPARISON Medvedev is too inflexible Moore is preferred, because of safe operation Mealy more flexible but danger of Spikes Unnecessary long paths (maximal clock period)

MEDVEDEV MACHINE Najeem Lawal, VHDL ET062G & ET063G Lecture 6 Output IS the state Two Processes architecture RTL of MEDVEDEV is... begin REG: process (CLK, RESET) begin -- State Registers Inference end process REG ; CMB: process (X, STATE) begin -- Next State Logic end process CMB ; end RTL ; One Process architecture RTL of MEDVEDEV is... begin REG: process (CLK, RESET) begin -- State Registers Inference with Logic Block end process REG ; end RTL ;

MEDVEDEV EXAMPLE Najeem Lawal, VHDL ET062G & ET063G Lecture 6 architecture RTL of MEDVEDEV_TEST is signal STATE,NEXTSTATE : STATE_TYPE ; begin REG: process (CLK, RESET) begin if RESET=`1` then STATE <= START ; elsif CLK`event and CLK=`1` then STATE <= NEXTSTATE ; end if ; end process REG; CMB: process (A,B,STATE) begin NEXTSTATE <= STATE ; case STATE is when START => if (A and B)=`0` then NEXTSTATE <= MIDDLE ; end if ; when MIDDLE => if (A and B)=`1` then NEXTSTATE <= STOP ; end if ; when STOP => if (A xor B)=`1` then NEXTSTATE <= START ; end if ; when others => NEXTSTATE <= START ; end case ; end process CMB ; --concurrent signal assignments for output (Y,Z) <= STATE ; end RTL ; Output IS the state

MEDVEDEV WAVEFORM Najeem Lawal, VHDL ET062G & ET063G Lecture 6 (Y,Z) = STATE => Medvedev machine Output IS the state

MOORE MACHINE Najeem Lawal, VHDL ET062G & ET063G Lecture 6 Three Processes architecture RTL of MOORE is... begin REG: -- Clocked Process CMB: -- Combinational Process OUTPUT: process (STATE) begin -- Output Logic end process OUTPUT ; end RTL ; Two Processes architecture RTL of MOORE is... begin REG: process (CLK, RESET) begin -- State Registers Inference with Next State Logic end process REG ; OUTPUT: process (STATE) begin -- Output Logic end process OUTPUT ; end RTL ; Output is a function of ONLY the state

MOORE MACHINE EXAMPLE Najeem Lawal, VHDL ET062G & ET063G Lecture 6 architecture RTL of MOORE_TEST is signal STATE,NEXTSTATE : STATE_TYPE ; begin REG: process (CLK, RESET) begin if RESET=`1` then STATE <= START ; elsif CLK`event and CLK=`1` then STATE <= NEXTSTATE ; end if ; end process REG ; CMB: process (A,B,STATE) begin NEXTSTATE <= STATE ; case STATE is when START => if (A and B)=`0` then NEXTSTATE <= MIDDLE ; end if ; when MIDDLE => if (A and B)=`1` then NEXTSTATE <= STOP ; end if ; when STOP => if (A xor B)=`1` then NEXTSTATE <= START ; end if ; when others => NEXTSTATE <= START ; end case ; end process CMB ; -- concurrent signal assignments for output Y <= ’1’ when STATE=MIDDLE else ‘0’ ; Z <= ‘1’ when STATE=MIDDLE or STATE=STOP else ‘0’ ; end RTL ; Output is a function of ONLY the state

MOORE MACHINE WAREFORM Najeem Lawal, VHDL ET062G & ET063G Lecture 6 (Y,Z) changes synchronous with STATE => Moore machine Output is a function of ONLY the state

MEALY MACHINE Najeem Lawal, VHDL ET062G & ET063G Lecture 6 Three Processes architecture RTL of MEALY is... begin REG: -- Clocked Process CMB: -- Combinational Process OUTPUT: process (STATE, X) begin -- Output Logic end process OUTPUT ; end RTL ; Two Processes architecture RTL of MEALY is... begin MED: process (CLK, RESET) begin -- State Registers Inference with Next State Logic end process MED ; OUTPUT: process (STATE, X) begin -- Output Logic end process OUTPUT ; end RTL ; Output is a function of state AND input

MEALY MACHINE EXAMPLE Najeem Lawal, VHDL ET062G & ET063G Lecture 6 architecture RTL of MEDVEDEV_TEST is signal STATE,NEXTSTATE : STATE_TYPE ; begin REG: process (CLK, RESET) begin if RESET=`1` then STATE <= START ; elsif CLK`event and CLK=`1` then STATE <= NEXTSTATE ; end if ; end process REG; CMB: process (A,B,STATE) Begin -- Like Medvedev and Moore Examples end process CMB ; -- concurrent signal assignments for output Y <= `1` when (STATE=MIDDLE and (A or B)=`0`) or (STATE=STOP and (A and B)=`0`) else `0` ; Z <= `1` when (STATE=START and (A and B)=`1`) or (STATE=MIDDLE) or (STATE=STOP and (A or B)=`1`) else `0` ; end RTL ; Output is a function of state AND input

MEALY MACHINE WAVEFORM Najeem Lawal, VHDL ET062G & ET063G Lecture 6 (Y,Z) changes with input => Mealy machine Notice the "spikes" of Y and Z in the waveform FSM has to be modeled carefully so there are no spikes in normal operation. Output is a function of state AND input Spike

EXAMPLE OF STATE MACHINE IN VHDL Najeem Lawal, VHDL ET062G & ET063G Lecture 6 architecture rtl of fsm_simple is type state_type is (start, r1, r2); signal state : state_type; begin -- rtl update_state : process (clk, reset) begin -- process fsm if reset = '0' then state <= start; elsif clk'event and clk = '1' then case state is when start => if A = '0' then state <= start; else state <= r1; end if; when r1 => if A = '0' then state <= r1; else state <= r2; end if; when r2 => if A = '0' then state <= r2; else state <= start; end if; end case; end if; end process update_state; output_logic : process(state) begin case state is when start => z <= '0'; when r1 => z <= '1'; when r2 => z <= '0'; end case; end process output_logic; end rtl; r2 z=0 start z=0 r1 z=1 A=0 A=1 A=0 A=1

MEALY TYPE IN VHDL Najeem Lawal, VHDL ET062G & ET063G Lecture 6 architecture mealy of fsm2 is type state is (S1, S2, S3, S4); signal present_state, next_state: state; begin process (aIn, present_state) begin CASE present_state IS when s1 => if (aIn = ’1’) then yOut yOut yOut if (aIn = ’1’) then yOut <= ’1’; next_state <= s2; else yOut <= ’0’; next_state <= s1; end if; end case; end process; process begin wail until clk = ’1’; present_state <= next_state; end process; end mealy; S1S4 S3S2 aIn=1/yOut=1 aIn=-/yOut=1 aIn=0/yOut=0 aIn=1/yOut=0 aIn=0/ yOut=1 aIn=-/ yOut=1 aIn yOut next_state present_state Output function

MOORE TYPE IN VHDL Najeem Lawal, VHDL ET062G & ET063G Lecture 6 library ieee; use ieee.std_logic_1164.all; entity fsm1 is port (aIn, clk: in std_logic; yOut: out std_logic); end fsm1; architecture moore of fsm1 is type state is (s1, s2, s3, s4); signal present_state, next_state: state; begin process (aIn, present_state) begin case present_state is when s1 => yOut yOut yOut yOut <= ’1’; if (aIn = ’0’) then next_state <= s1; end if; end case; end process; process begin wait until clk = ’1’; present_state <= next_state; end process; end moore; S1S2 S4S3 yOut=0 aIn=0 yOut=0 yOut=1 aIn=0 aIn=1

COMPONENTS IN AN DIGITAL DESIGN Najeem Lawal, VHDL ET062G & ET063G Lecture 6 A digital design consists of –At least one control unit (FSM) –At least one datapath unit For example, adder, multiplier, comparator Register for temporary storage of variables Often a design consists of many controllers and datapaths Design model: FSM with datapath –Describes the function of the designs containing both control unit and datapath

FSM WITH DATAPATH Najeem Lawal, VHDL ET062G & ET063G Lecture 6 Control unit Datapath Control signals Status signals Control inputs control outputs Data inputs Data outputs FSMD control inputs Data inputs control outputs Data outputs

DESIGN EXAMPLE Najeem Lawal, VHDL ET062G & ET063G Lecture 6 DESIGN A FUNCTION COMPUTING: TypeDescription#bits Din, datavalues, positive integer, for a, x and b in sequence8 startin, controlActivate computation of Y, active high1 busyout, controlindicate that unit is busy computing1 Yout, dataThe computed value Y17 resetin, controlInitialize the unit1 Y=25 a = 5 x = 3b = 10 D start clk busy Y

CONT. DESIGN EXAMPLE Najeem Lawal, VHDL ET062G & ET063G Lecture 6 Y = a·x + b D start reset clk Y busy Control unit Datapath D Y resetstart busy storeA storePr External control signals Controlling the unit External control signal internal control signals External data signals

CONT. DESIGN EXAMPLE Najeem Lawal, VHDL ET062G & ET063G Lecture 6 start getA multAX addB Start=0 Start=1 busy = 0 storeA = 0 storePr = 0 busy = 1 storeA = 1 storePr = 0 busy = 1 storeA = 0 storePr = 1 busy = 1 storeA = 0 storePr = 0 × + EN D Y clk storeA storePr A X A×X B A×X+B

SUMMARY Najeem Lawal, VHDL ET062G & ET063G Lecture 6 ALL DIGITAL DESIGNS FOLLOW THE MODEL OF FSMD DESIGN FLOW –Specify the algorithm to be implemented –Identify Which components are needed in the datapath Which states are needed in the control unit Which control signals are needed to the datapath Which status signals are needed to the control unit –Develop State Transition Graph for the control unit Block diagram for the data path

QUESTIONS Najeem Lawal, VHDL ET062G & ET063G Lecture 5 ABOUT FPGA / VHDL ABOUT VGA DISPLAY / TIMING ABOUT IMAGE SENSOR TIMING ABOUT RANGE SENSOR ABOUT LINE BUFFERS ABOUT MEMORIES & COUNTERS

END OF LECTURE 6 Najeem Lawal, VHDL ET062G & ET063G Lecture 5 OUTLINE –Range Sensor display –FSM in VHDL Medvedev FSM Moore FSM Mealy FSM –FSMD – FSM and Data path

TESTBENCH IMAGES Najeem Lawal, VHDL ET062G & ET063G Lecture 5

RANGE SENSOR Najeem Lawal, VHDL ET062G & ET063G SRF –10us pulse to the Trigger input –50ms period between each Trigger pulse –Mode 1 recommended

PROJECT IMPLEMENTATION Najeem Lawal, VHDL ET062G & ET063G CONTROLLER IS FPGA –System Clock and Exposure are generated –Understand timing diagrams and implement the project.

SLIDING WINDOW Najeem Lawal, VHDL ET062G & ET063G –An image is read from left to right and top to bottom sliding –Given an algorithm with many tasks O(x,y) = F(x,y) x I(x,y) –Some of the task are neighbourhood oriented sliding window N x M sliding window. N and M are odd numbers

SLIDING WINDOW Najeem Lawal, VHDL ET062G & ET063G Suggested implementation architecture 1.linebuffers 2.Boundary controller 3.Pixel switch 4.Filter function 5.Output synchronisation

SLIDING WINDOW Najeem Lawal, VHDL ET062G & ET063G –At the image edges –There are invalid pixel –How do you build a valid neighbouthood of pixels around edge pixels? –3 alternatives Avoid processing edge pixels Copy centre pixel to the invalid pixel locations Reflections. Default to 0 or 255