1 1 JEITA STD-TSC updates JEITA EDA standardization subcommittee, Vice chair IEC TC93 WG2, Co-convener NEC System Technologies Satoshi Kojima IEEE-DASC meeting at DVCon2010, San Jose 7:30 -9:00, 25 th February 2010 at SpringSoft Office

2 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA Introduction  Organization chart and updates of STD-TSC Some concerns on DASC activities  Design language harmonization  BVDL: the Bird’s-eye View for Design Languages Summary Summary - Outline -

3 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA JEITA Structure and Management Japan Electronics and Information Technology Industries Association JEITA Policy and Strategy Board Environment Board Consumer Electronics Board IT and Industrial Systems Board Display Devices Board Electronic Components Board Semiconductor Board (JEITA-JSIA) Semiconductor Industrial Affairs Committee Semiconductor International Affairs Committee Semiconductor Technology Committee Marketing Committee Road Map Committee EDA Technical Committee (EDA-TC) - Member : 16 Companies Fujitsu ML, Panasonic, NEC EL, Toshiba, Renesas, Rohm, Sanyo, Sharp, Sony, Seiko Epson, Synopsys, JEDAT, Mentor, Ricoh, Toppan, Zuken Elmic

4 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA EDA-TC Structure in fiscal year 2009 EDA Technical Committee EDA Standardization Technical Sub-Committee SystemC Working Group NPD (Nano-scale Physical Design) Working Group EDSFair 2010 Executive Committee Acceleration of Standardization Solution for Technical Challenges Promotion of EDA Technology Chair: Ohta (Panasonic) Chair : Saito (SONY) Chair: T.Kanamoto (Renesas) Chair : Yamamoto (OKI Semicon Chair : Imai (Toshiba) Power Format Working Group Chair : T.Nakamori (Fujitsu ML) Vice-chair : Aono (EPSON) Kojima (NECST) in Rohm Group)

5 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA Members: semiconductor vendors, EDA vendors and academia  Chair: Yamamoto (OKI Semicon in Rohm Group)  Vice-chairs: Aono (EPSON), Kojima (NECST) To reflect opinions on technical and business issues as a group of EDA power users to De Jure standard bodies such as IEEE and IEC TC93 To raise issues on design flows to solve today and future design challenges from the member companies and to propose what standards can contribute to solve them Two subsidiaries are actively working on  SystemC Working Group  Power Format Working Group EDA Standardization TSC Activities

6 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA Yamamoto-san took leadership to finalize BVDL: the Bird’s- eye View for Design Languages and shared with members of IEC TC93 at Kyoto meeting in late September, Now working on Fiscal Year 2010 plans  The chair might succeed to Imai-san in Toshiba from Yamamoto-san.  Power Format WG might make a pause since they accomplished the goal.  A new WG will be formed and aim to harmonize co-design environment among LSI, Package and Board. Fukuba-san in Toshiba and his team have been intensively making preparation. EDA Standardization TSC Activities (Cont’d)

7 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA Collaboration w/IEEE and IEC Domestic collaboration  To dispatch a chair and some experts to WG2 of IEC TC93 JNC in IEICE (The Institute of Electronics, Information and Communication Engineers) and to lead the activities of the WG2 JNC Global collaboration  Worked with P1800WG (SystemVerilog), P1666WG (SystemC) and P1801WG (Power format) in IEEE-DASC, reviewing the drafts and participating in the balloting. Planning work with P1481(SSPEF)  Has been a member of IEEE-SA since 2004 and participated in balloting such as IEEE1800, IEEE1666 in 2005 and IEEE1801 in 2008  Kojima has been a JEITA DR of IEEE DASC since 2008  Kojima has been a Co-convener of TC93 WG2 since 2000 and worked with Dennis Brophy in USNC  IEEE-IEC Dual Logo agreement made in 2003 accelerates EDA global standardization such as SytemC, System Verilog…

8 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA IEICE TC93 JNC JEITA EDA STD-TSC WG2 JNC IEEE IEEE-SA IEC TC93 Int’l WG2 Accellera, OSCI WG2 JNC EDA-TC WGs (P1666, P1801, P1481, …) DASC CAG NesCom, RevCom SC-WG PF-WG NPD-WG Membership Hand-offs Collaboration Collaboration scheme Dual Logo agreement Representatives

9 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA EDA standards provide a mechanism for defining common semantics for integrated design systems among various tools To define common SoC design flow and then categorize existing and emerging standards To set strategies of EDA standardization activities for every category JEITA to set strategies of EDA standards System Design Analyze Implement w/Opt. Equivalence check Circuit Logic Software Scan/BIST Place Route DFM DFT Noise Power Timing Area Communicate Libraries Verification Data for manufacturing Testability Performance Function Specification (Function + Constraints)

10 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA Design languages harmonization JEITA had some good lessons-learned through power format standardization activities under 2 formats issues of UPF and CPF  Criteria to qualify De Jure standard is applicable for practical SoC design flow or not  Unification is best, but in reality interoperability and harmonization are indispensable An AMS language is derived from a digital design language to cover digital- analog mixed signal world. In result, there are three AMS languages in an EDA community  VHDL-AMS is IEEE standard and might be in an academia  Verilog-AMS might be De Facto standard in the market  SystemC-AMS will be OSCI standard soon

11 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA Bird’s-eye view for Design Languages BVDL aims to make full use of planning and decision-making on JEITA activities and to facilitate global understanding of various design languages, classified into De Jure standards, Forum standards and De Facto standards BVDL is a set of charts to show the position that each design language occupied in the design technology along a generally accepted design flow  The X-axis shows design phases of the flow  The Y-axis shows design objects which is a set of design data such as hardware description, verification description, design constraints and so on Current status  We have created the first version of BVDL  We will use it for upcoming 2010 fiscal year planning

12 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA How to read BVDL.Design flow (X-axis) Design Flow (X-Axis) Analog Functional Design Analog Architecture Design Post-Layout Circuit Verification The X-axis of BVDL’s chart corresponds to design flow. The languages used in each design step of the flow are shown. Design languages that are used in “Analog Functional Design, Analog Architecture Design” phase are shown here.

13 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA How to read BVDL.Design objects (Y-axis) Design Objects (Y-Axis) The Y-axis of BVDL’s chart corresponds to design objects. The design objects that are defined in each language are marked with a cross.

14 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA BVDL consists of four charts. To make BVDL easy to grasp, we divided BVDL into four charts. Each chart corresponds to one of the four major design processes. BVDL (Four charts) 1. Electronic System Design 2. SoC Design 3.1 Analog Block Design 4. Characterization / IP Preparation 3.2 Mixed-Signal Verification SoC Manufacturing IP Development (Subset of SoC Design Process) Electric System Manufacturing Design Process 1. Electronic System Design2. SoC Design 3.1 Analog Block Design 3.2 Mixed-Signal Verification 4. Characterization, IP Preparation

15 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA The Four Major Design Processes Electronic System Design Electronic System Design is a design process to develop electronic systems. The Electronic System Design chart of BVDL describes interface with SoC design mainly. This is because JEITA EDA-TC’s activity is primarily for semiconductor industry. SoC Design SoC Design is a design process to develop System-on-Chips. The SoC Design chart of BVDL describes only digital part of SoC design. This is to make the chart easy to understand. Analog circuits are developed in the Analog Block Design process and are imported as blocks. This is not always true. But it is NOT worthy to create a perfect definition of total design process for our purpose.

16 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA The Four Major Design Processes(cont’d) Analog Block Design / Mixed-Signal Verification Analog Block Design is a design process to develop analog blocks. The blocks developed in this process are provided to the SoC design flow through “Characterization / IP Preparation” process. Mixed-Signal Verification is the process to verify the interface between the digital portions and the analog portions. Characterization / IP Preparation “Characterization / IP Preparation” is a design process to prepare data of analog blocks and IPs. The prepared data in this process are provided to other design processes. The languages for the interface data are collected, but the definitions of this process is under discussion now.

17 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA How to use BVDL.Example-1. Case Two languages exist in the same design phase and define the same design objects. Example:UPF and CPF Action Candidates. Clarify the difference of the languages. Minimize the obstacles to keep interoperability of the languages.

18 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA How to use BVDL.Example-2. Case Technology shift from lower level to higher level. Example:“RTL Compile” and “C Compile” Action Candidates. Learn from old technology and make plan for new technology. Equivalence Check Design Descriptions (RT-Level) Design Constraint (SDC, UPF) RTL CompileStyle Check Constraint Check Design Descriptions (Gate-Level) RTL Compile (Old Technology) C Compile (New Technology) Do we define the design description language enough for C compile and Equivalence Check? Are design constraint languages ready for practical purposes?

19 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA Future Plan Today, we introduced our BVDL as one of our activities. Purpose. For planning and decision making on our standardization activities. To accomplish global understanding of design languages. Future Plan We will put the finishing touch to our BVDL. We will use it for the coming 2010 fiscal year planning.

20 Copyright(C) JEITA 2008 IEEE-DASC at DVCon2010, 25Feb2010© Copyright 2010 JEITA Summary To update JEITA standardization activities such as STD-TSC, SystemC WG, and Nano-scale physical design WG To talk about some concerns on DASC activities Design languages harmonization BVDL introduction

21 JEITA : Japan Electronics and Information Technology Industries Association ( URL EDA-TC : EDA Technical Committee ( URL