A tour of the chip D.G.Ast. Not well aligned ! Transistors T1 and T2 share a gate contact. The smallest transistors is T4. To right is the first Diode.

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Presentation transcript:

A tour of the chip D.G.Ast

Not well aligned ! Transistors T1 and T2 share a gate contact. The smallest transistors is T4. To right is the first Diode Below is inverter 1

Diodes D1 and D2. They look nearly the same. The reaction of the Al indicates that D1 the Al is likely in contact with implanted Si. And in D2 in contact with the n-type substrate. It will become clear in the electrical test. Below D2 is the gate oxide capacitor and below D1 the field oxide capacitor

Capacitors C1 and C2. C2 is about 3 times the diameter of C1. \ Since the FOX is 10 times as thick as the gate oxide, C2 has a 10 times larger area (3 times the diameter). This scaling ensures that both caps have similar capacitance in a range easily measured (around 100 pF)

Inverters I1 and I2. An inverter is 2 transistors in series. Note that the two gates are not the same size for reasons you will learn in a layout class.

The chips at the periphery contain single crystal MEMS. This here is a floating grid suspended on Si springs that can driven sideways (x-y) by comb drives. The p+ implanted beams are not etched by KOH. KOH is an anisotropic etch that stops at {111} planes.

Single beam (left) and and a platform with comb drives. The platform is held be a single beam. You can drive the thing into resonance !

There are many more structures on the chip you processed - Kelvin resistance probes, test structures to measure the implant sheet resistance, logic blocks…. THE END