0 iNEMI Board and System Manufacturing Test TIG Update Phil Geiger 2008 IEEE Board Test Workshop Sep 08

1 iNEMI Overview The International Electronics Manufacturing Initiative (iNEMI) is an industry-led consortium whose mission is to assure leadership of the global electronics manufacturing supply chain. iNEMI roadmaps the needs of the global electronics industry, identifies technology and infrastructure gaps and helps eliminate those gaps (both business and technical) through: –accelerated deployment of new technology –development of industry infrastructure –dissemination of efficient business practices –stimulation of standards

2 iNEMI Test TIG iNEMI Board and System Manufacturing Test TIG Goals: To improve the effectiveness of the test process and the quality of electronic products in a global manufacturing environment Scope includes test technology and process improvement for boards and systems (e.g. automated inspection, electrical test, boundary scan, functional test, system test)

3 iNEMI Test TIG The iNEMI Test TIG was initially formed by representatives of a group of companies (HP, Intel, Apple, Cisco, Dell) with the purpose of exploring solutions to common global manufacturing board and system test related challenges facing the OEMs and the industry in general. Test TIG Chair: Rosa Reinosa, Hewlett-Packard Test TIG Co-Chair: James Grealish, Intel

4 Test TIG Projects 2008/2009 Projects: Functional Test Coverage Model Boundary Scan Adoption Board Flexure

5 Functional Test Coverage Model The goal of the functional test coverage model project is to develop a common industry methodology for predicting functional test coverage on a system board. Chair: Tony Taylor, Intel

6 Functional Test Coverage Model Project Milestones: The first phase of this project is to look at common industry practices today The second phase is to develop a methodology to capture test coverage for functional test The third phase of the project is to exercise the method with existing product boards (server, networking and medical) and to evaluate the effectiveness of the methodology and any gaps that would need to be addressed. First pass conclusions will be available in early 2009.

7 Functional Test Coverage Model Status: First product assessment method in progress Currently applying methodology on 3 product boards Next Steps: Gather learnings from first assessment Modify methodology based on learnings Complete two other assessments Refine and finalize model Publish results Publish model via iNEMI

8 Boundary Scan Adoption The goal of the boundary scan adoption project is to broaden the use of boundary scan technology in the industry. The project is addressing the importance that Boundary Scan has in enabling the test of component interconnects that may not be able to be tested any other way. Many OEMs are faced with the unique challenge of testing these complex components that lack testability features. Chair: Phil Geiger, Dell Co-chair: Steve Butkovich, Cisco

9 Boundary Scan Adoption Project Milestones: The first phase of this project seeks to identify the state of boundary scan technology use in the industry. The team will develop a comprehensive survey to gather inputs from component vendors, OEMs, ODMs and CMs. The second phase is to distribute the survey and collect and analyze the results. Survey results will be published through iNEMI. The third phase of the project will include actions to address major industry gaps found through the survey.

10 Boundary Scan Adoption Status: Currently in Phase 1 Generating draft of industry survey Next Steps: Complete draft of industry survey Send out industry survey Analyze survey inputs Publish results Address initial set of gaps

11 Board Flexure The goal of the board flexure project is to promote the use of standard methodologies to establish strain limits for BGA components and printed circuit boards. Lead free boards are more susceptible to mechanical stresses and therefore more prone to damage when bent. There is currently no consistency in the industry about the placement of gauges on boards to measure strain levels due to the real estate challenges on board designs, test methods to derive strain limits vary, as well as, strain metrics and failure criteria. Chair: Rosa Reinosa, HP

12 Board Flexure Project Milestones: A new emerging spherical bend test methodology originally developed by Intel will be proposed to IPC/JEDEC 97XX committee –This new test method can better emulate worst bend mode/conditions on a PCA during manufacturing, test or assembly process. –Variables that drive strain limit will be highlighted so that designers and engineers can improve board, product and test fixture designs, as well as, handling practices to minimize mechanical damage. New lead free PCA strain limit guidance will be published. –Each company will continue to establish specific guidelines for components and boards based on their own analysis and level of risk. The group expects to have the first proposal for IPC/JEDEC in late Project completion is expected in 2009.

13 Board Flexure Status: Spherical Bend Test Method Standard proposal under development Completed review of IPC 9702 challenges and recommendations Next Steps: Review IPC 9704 challenges and recommendations Present new test method proposal to IPC 97XX committee and JEDEC 14.1 (late 2008) Complete enhancements to IPC 9702 and IPC 9704 Submit recommendations to IPC and JEDEC committee

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