Memory/Storage Architecture Lab Computer Architecture Pipelining Basics.

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Presentation transcript:

Memory/Storage Architecture Lab Computer Architecture Pipelining Basics

2 Memory/Storage Architecture Lab 2 Sequential Processing

3 Memory/Storage Architecture Lab 3 Pipelined Processing

4 Memory/Storage Architecture Lab 4 Basic Steps of Execution 1. Instruction fetch step (IF) 2. Instruction decode/register fetch step (ID) 3. Execution/effective address step (EX) 4. Memory access (MEM) 5. Register write-back step (WB)

5 Memory/Storage Architecture Lab 5 Pipelined Instruction Execution  Sequential Execution  Pipelined Execution ADD $3, $1, $2 SUB $4, $5, $6 AND $7, $8, $9

6 Memory/Storage Architecture Lab 6 Basic Pipeline

7 Memory/Storage Architecture Lab 7 Major Hurdles of Pipelining  Structural Hazard  Data Hazard  Control Hazard

8 Memory/Storage Architecture Lab 8 Structural Hazard IFIDEXMEMWB IFIDEXMEMWB IFIDEXMEMWB IFIDEXMEMWB

9 Memory/Storage Architecture Lab 9 Solutions to Structural Hazard  Resource Duplication example − Separate I and D caches for memory access conflict − Time-multiplexed or multi-port register file for register file access conflict

10 Memory/Storage Architecture Lab 10 Data Hazard (RAW hazard) ADD $1, $2, $3 SUB $4, $1, $5 R IFMEMEX ID W WB R IFMEMEX ID W WB Time

11 Memory/Storage Architecture Lab 11 Solutions to Data Hazard  Freezing the pipeline  (Internal) Forwarding  Compiler scheduling

12 Memory/Storage Architecture Lab 12 Freezing The Pipeline  ALU result to next instruction  Load result to next instruction R IFMEMEX ID W WB ADD $1, $2, $3 SUB $4, $1, $5 stallIF R ID stallEX R IFMEMEX ID W WB LW $1, 32($6) SUB $4, $1, $5 stallIF R ID stallEX

13 Memory/Storage Architecture Lab 13 (Internal) Forwarding  ALU result to next instruction (Stall X)  Load result to next instruction (Stall 1) R IFMEMEX ID W WB ADD $1, $2, $3 SUB $4, $1, $5 R IFMEMEX ID W WB LW $1, 32($6) SUB $4, $1, $5 R IFMEMEX ID W WB stall R IFMEMEX ID

14 Memory/Storage Architecture Lab 14 Control Hazard  Caused by PC-changing instructions (Branch, Jump, Call/Return) For 5-stage pipeline, 3 cycle penalty 15% branch frequency. CPI = 1.45

15 Memory/Storage Architecture Lab 15 Solutions to Control Hazard  Optimized branch processing  Branch prediction  Delayed branch

16 Memory/Storage Architecture Lab 16 Optimized Branch Processing 1. Find out branch taken or not early → simplified branch condition 2. Compute branch target address early → extra hardware

17 Memory/Storage Architecture Lab 17 Branch Prediction  Predict-not-taken

18 Memory/Storage Architecture Lab 18 Delayed Branch  Semantics of delayed branch

19 Memory/Storage Architecture Lab 19 Delayed Branch