ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

F. Anghinolfi 3, W. Bialas 4, N. Busek 8, A. Ciocio 1, D. Cosgrove 2, V. Fadeyev 1, C. Flacco 2, M. Gilchriese 1, A. Grillo 2, C. Haber 1, J. Kaplon 3, C. Lacasta 5, W. Murray 7, H. Niggli 8, T. Pritchard 6, F. Rosenbaum 2, T. Stezelberger 1, H. Spieler 1, C. Vu 1, M. Wilder 2, H. Yaver 1, F. Zetti 1 1 Lawrence Berkeley National Laboratory, Berkeley, California, USA 2 SCIPP, University of California Santa Cruz, USA 3 CERN, 1211 Geneva 23, Switzerland 4 Faculty of Physics and Nuclear Techniques, UMM, Cracow, Poland 5 Instituto de Fisica Corpuscolar, IFIC, Valencia, Spain 6 Queen Mary and Westfield College, University of London, UK 7 Rutherford Appleton Laboratory, Didcot, UK 8 Formerly at LBNL

ATLAS is a hadron collider experiment at CERN 60 m 2 of silicon strip detectors

ABCD3T: 128 readout channels rad-hard DMILL technology works at 40 MHz binary readout analog front-end with amplifiers and comparators 132-deep digital pipeline and communication circuitry edge or level sensing mode sparsification 3-bit trim DACs for channel matching after irradiation

Scheme of the dataflow:

Test System Hardware Components

Test setup at Rutherford Appleton Laboratory, UK

Control GUI

The ABCD3T wafers are screened, and a sample of good chips is selected for the experiment on the basis of the following tests:  Analog  Digital  Power Consumption  Internal DACs linearities  I/O Signals

Analog Tests Have binary readout => need to make lots of threshold scans to extract gain, noise, offset and measure trim DAC linearity for all channels. Threshold scan Noise vs Channel Number To speed up the testing, FPGA chip on the VME board is programmed to: - issue sequences of ABCD3T input commands, - interpret the data from the chip and store the number of hits per channel in memory chips. Only threshold scan histogram is read out.

Digital Tests We use test vectors to test the following features of the ABCD3T:  Configuration register R/W operations,  Addressing, beam counter, error codes,  Data compression logic,  Dynamic and static pipeline,  Redundant command line,  Data/token (by)passing. The comparison of the chip response with the results of Verilog simulation of the ABCD3T is done inside the FPGA, only binary yes/no result is read out. All test vectors are run while scanning Vdd. Frequency scan is made from 40 MHz to 90 MHz to model the effect of radiation damage.

I/O Signal Tests We test I/O signal properties by stimulating them with test vectors: - find the phases, relative to the clocks, using delay chips, - scan the swing of the input signals to find minimal working value, - scan the thresholds of the window comparators to measure the swing the output signals. Distribution of dataout signal phase relative to input clock for digitally good chips on a wafer

The tester is deployed three testing sites:  University of California at Santa Cruz  Rutherford Appleton Laboratory, UK  CERN, Switzerland The performance of the systems has been verified using a common set of reference wafers. The yield was found to agree within 1% for all test sites. The test time was optimized. Screening of one wafer with 256 ABCD3T chips takes 5 hours.