Active Packaging: Power Management for Nanoprocessors Raj Nair, ComLSI Inc. Presented to the First AZ Nanotechnology Symposium March 16, 2006.

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Presentation transcript:

Active Packaging: Power Management for Nanoprocessors Raj Nair, ComLSI Inc. Presented to the First AZ Nanotechnology Symposium March 16, 2006

Prologue With a “billion connected pc’s,” cutting nanoprocessor power by ½ reduces energy consumption by 50 Giga watts! Advanced power management is innovation leading to energy efficiency

Scaling of Dimensions Smaller, faster & cheaper… Or so it was!

Power Related Prediction in ’71’74’78’85’92’00’04’08 Power (Watts) Pentium® processors Processor power doubles every ~36 months… References: Raj Nair 2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’ 2002 Intel Technology Journal paper “Emerging Directions for Packaging…”

Consequences

Leakage in Nanometer CMOS… Drain induced barrier lowering in short channel devices make leakage increase with Vds (Vdd) Sub-threshold channel leakage dominates the Vdd dependent leakage. Source: S. Narendra & A. Chandrakasan Leakage in Nanometer Technologies, Springer Publications, 2005 Leakage power now equals active power! And both are exponential with Vdd…

Supply Voltage Is Key Lower supply voltage = much lower power Active power is quadratically related (  V 2 ) Leakage power is similarly dependent upon V n, n > 2 For a Nanoprocessor (or SoC), this is multiple supplies on chip & independent dynamic control And fine, high-bandwidth control of noise…

Active Noise Regulators Active Noise Regulators (ANR’s) sense/regulate noise in a nanoprocessors’s voltage islands ANR’s enhance (not replace) nanoprocessor power delivery infrastructure Reference: Raj Nair & Donald Bennett Power Management Designline article

Active Noise Regulation Chip power grid noise ANR attached to top left corner of grid

Prediction & Validation  2001 iATTJ [1] “The Silicon Sandwich integrates all the components for power conversion into a multi–component active interposer that is bonded to the CPU and ‘sandwiched’ between two heat sinks. The name derives from the structure and the many technologies integrated.” $2006 EETimes [3] “A second ISSCC paper discusses a prototype method for supporting multiple power supply rails on chip by using a new all- CMOS, fast voltage regulator. … The technique would be especially useful for running different cores at different supply voltages on multicore CPUs, Rattner said. "This is a very important technology for which we have high hopes," he added. … Bringing the new thin films into high volume fabs and getting the inductors on chip are major challenges toward commercializing the technology over the next three to four years, he added.” References: [1], [2] Raj Nair, [3] EETimes article 2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’ / US pat. pub February 06, 2006 EETimes Intel CTO calls for better chip-design tools to beat process varianceIntel CTO calls for better chip-design tools to beat process variance

ComLSI Products / Service offering PowerESL: Tools and expertise for IC power integrity Analog / Mixed-Signal IP in development for DVI / HDMI / Power Management applications Analog / Custom design services Patents: 5 pending in ANR / AVP technology 40+ authored, 34 issued Team: 50+ years of technology mgmnt. & mktg. Contact: Raj Nair, President, (480)