Pixel Chip Testing S. Easo, RAL 10-1-2001 Current Status of the Pixel Chip Testing. Plans for an LHCb Test Setup at CERN.

Slides:

Advertisements

Similar presentations

20/Oct./2000 CF IEEE NSS 2000 at Lyon,France 1 An MWPC Readout Chip for High Rate Environment Introduction ASIC Structure & Fabrication ASIC Evaluation.

Advertisements

MICE Fiber Tracker Electronics AFEII for MICE (Front end readout board) Recall: AFEs mount on ether side of the VLPC cass, with fibers going to the VLPCs.

DOE/NSF Review of ATLAS, 1 Mar 2000, BNL Muon MDT Front End Electronics (WBS 1.5.9) James Shank DOE/NSF Review of U.S. ATLAS Detector (with help from:

1 MICE Tracker Readout Update, Preparation for Cosmic Ray Tests Introduction/Overview AFE-IIt firmware development VLSB firmware development Hardware progress.

6 June 2002UK/HCAL common issues1 Paul Dauncey Imperial College Outline: UK commitments Trigger issues DAQ issues Readout electronics issues Many more.

Uli Schäfer 1 JEM: Status and plans JEM1.2 Status Test results Plans.

Status of Oxford Setup Matthew Chalk, Erik Devetak, Johan Fopma, Brian Hawes, Ben Jeffery, Nikhil Kundu, Andrei Nomerotski University of Oxford ( 18 August.

Large Area, High Speed Photo-detectors Readout Jean-Francois Genat + On behalf and with the help of Herve Grabas +, Samuel Meehan +, Eric Oberla +, Fukun.

MICE Workshop Sept 2004 AFEII for MICE Recall: AFEs mount on ether side of the VLPC cass, with fibers going to the VLPCs between them. AFE has 8 identical.

Trigger-less and reconfigurable data acquisition system for J-PET

Uli Schäfer 1 JEM1: Status and plans power Jet Sum R S T U VME CC RM ACE CAN Flash TTC JEM1.0 status JEM1.1 Plans.

1 CARRIER BUS LAYOUT(a) ± 193 mm ladder1ladder mm mm Pixel chip Michel Morel EP/ED 09/ x 425µ 256 x 50µ Decoupling capacitors

Peter Chochula CERN-ALICE / Dpt. Of Nucl. Physics MFF UK Bratislava Queued... HTTP IPX,SPX Component Client Component Client COM Component Client COM DCE-RPC.

MICE Tracker Readout and Data Acquisition; Solenoid Magnetic Field Measurement Terry Hart for the MICE Collaboration, Illinois Institute of Technology,

MEDIPIX3 TESTING STATUS R. Ballabriga and X. Llopart.

Mathieu Goffe EUDET JRA1 meeting, DESY Wednesday 30 January 2008 IPHC, 23 rue du Loess BP 28, 67037, Strasbourg Cedex 02, France.

Mass production testing of the front-end ASICs for the ALICE SDD system L. Toscano a, R. Arteche Diaz b,d, S. Di Liberto b, M.I. Martínez a,c, S.Martoiu.

Mark Raymond /10/051 Trip-t testing brief status report test setup description - hardware and software some very early results.

Trigger Supervisor (TS) J. William Gu Data Acquisition Group 1.TS position in the system 2.First prototype TS 3.TS functions 4.TS test status.

Status of Detector Prototype (for Hawaii meeting at Big Island) August 24, 2002 Yee Bob Hsiung For Koji Ueno, Yuri Velikzhanin Yanan Guo and Eddie Huang.

MR (7/7/05) T2K electronics Beam structure ~ 8 (9?) bunches / spill bunch width ~ 60 nsec bunch separation ~ 600 nsec spill duration ~ 5  sec Time between.

C.Schrader; Oct 2008, CBM Collaboration Meeting, Dubna, Russia R/O concept of the MVD demonstrator C.Schrader, S. Amar-Youcef, A. Büdenbender, M. Deveaux,

Status of the Beam Phase and Intensity Monitor for LHCb Richard Jacobsson Zbigniew Guzik Federico Alessio TFC Team: Motivation Aims Overview of the board.

LNL 1 SLOW CONTROLS FOR CMS DRIFT TUBE CHAMBERS M. Bellato, L. Castellani INFN Sezione di Padova.

Phase-1 Design. i PHC Phase /04/2008 System Overview Clock, JTAG, sync marker and power supply connections Digital output.

June 3, 2005H Themann SUSB Physics & Astronomy 1 Phenix Silicon Pixel FEM S. Abeytunge C. Pancake E. Shafto H. Themann.

Yuri Velikzhanin NuTel TV meeting, June 13 (Friday), 2003 Status of electronics for NuTel prototype.

1 HO Upgrade: QC and Production Preparation in India Shashi Dugad India-CMS Meeting, BARC 30 July 2010.

Status of the MaPMT o Status quo o Ongoing work o Issues – mechanics – electronics – schedule o Conclusions LHCb meeting Milano Franz Muheim.

John Coughlan Tracker Week Feb FED Status FED Production Status Transition Card.

EP/ED group meeting1 ALICE PIXELS DETECTOR.

1 VeLo L1 Read Out Guido Haefeli VeLo Comprehensive Review 27/28 January 2003.

FED RAL: Greg Iles5 March The 96 Channel FED Tester What needs to be tested ? Requirements for 96 channel tester ? Baseline design Functionality.

24/03/2010 TDAQ WG - CERN 1 LKr L0 trigger status report V. Bonaiuto, G. Carboni, L. Cesaroni, A. Fucci, G. Paoluzzi, A. Salamon, G. Salina, E. Santovetti,

John Coughlan Tracker Week October FED Status Production Status Acceptance Testing.

Final FED 1 Testing Set Up Testing idea and current status Preliminary results Future development Summary M. Noy

Test Setup for FE-I3 single chips / modules, FE-I4_proto1 and for full scale FE-I4 Marlon Barbero, Bonn.

L. Greiner 1St. Odile CMOS Workshop – September 6-9, 2011 STAR HFT LBNL Leo Greiner, Eric Anderssen, Thorsten Stezelberger, Joe Silber, Xiangming Sun,

DAQ Status for cosmic-ray test in RAL Hideyuki Sakamoto MICE Phone meeting 12 th July 2007 Contents Status Setup for cosmic-ray test bench Schedule.

IPHC - DRS Gilles CLAUS 04/04/20061/20 EUDET JRA1 Meeting, April 2006 MAPS Test & DAQ Strasbourg OUTLINE Summary of MimoStar 2 Workshop CCMOS DAQ Status.

Tracker Week October CCLRC, Rutherford Appleton Laboratory, Oxon, UK Imperial College, London, UK Brunel University,

Status report of test procedures for the readout pixel chips in Catania F.Riggi ITS Meeting, June 2002.

Trip-t testing progress report

ERC - Elementary Readout Cell Miguel Ferreira 18 th April 2012

Status of the n-XYTER testing Knut Solvag, Gerd Modzel, Christian Schmidt, Markus Höhl, Andrea Brogna, Ullrich Trunk, Hans-Kristian Soltveit CBM.

HBD/TPC Electronics Status Works done to for a)Prototype detector readout b)Understand packing density and heat loading issues c)Address the overall system.

1 Test Setups for the FE-I4 Integrated Circuit Stewart Koppell 8/1/2010.

B.Satyanarayana Department of High Energy Physics Tata Institute of Fundamental Research Homi Bhabha Road, Colaba, Mumbai,

1 MICE Tracker Readout Update Introduction/Overview TriP-t hardware tests AFE IIt firmware development VLSB firmware development Hardware progress Summary.

11 October 2002Paul Dauncey - CDR Introduction1 CDR Introduction and Overview Paul Dauncey Imperial College London.

ALIBAVA system upgrade Ricardo Marco-Hernández IFIC(CSIC-Universidad de Valencia) 1 ALIBAVA system upgrade 16th RD50 Workshop, 31 May-2 June 2010, Barcelona.

HBD/TPC Electronics Status Works done to for a)Prototype detector readout b)Understand packing density and heat loading issues c)Address the overall system.

Tracker Week February presented by John Coughlan RAL FED Status FEDv2 Testing Pre-Series Manufacture Final Production.

.1PXL READOUT STAR PXL READOUT requirement and one solution Xiangming Sun.

M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June Status of the PINT chip M. Adinolfi University of Oxford.

Notes on visit to Rome 28/04/2014 Christian Joram Szymon Kulis Samir Arfaoui.

Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.

DAQ 1000 Tonko Ljubicic, Mike LeVine, Bob Scheetz, John Hammond, Danny Padrazo, Fred Bieser, Jeff Landgraf.

Vladimir Zhulanov for BelleII ECL group Budker INP, Novosibirsk INSTR2014, Novosibirsk 2014/02/28 1.

DHH Status Igor Konorov TUM, Physics Department, E18 PXD DAQ workshop Münzenberg –June 9-10, 2011.

SVD FADC Status Markus Friedl (HEPHY Vienna) Wetzlar SVD-PXD Meeting, 5 February 2013.

Understanding of SKIROC performance T. Frisson (LAL) On behalf of the SiW ECAL team Special thanks to the electronic and DAQ experts: Stéphane Callier,

Setup for automated measurements (parametrization) of ASD2 chip

Readout System of the CMS Pixel Detector

AFE II Status First board under test!!.

Roberto Dinapoli CERN-CEM II,Montpellier For the ALICE Collaboration

Status of n-XYTER read-out chain at GSI

The CMS Tracking Readout and Front End Driver Testing

Setup for testing LHCb Inner Tracker Modules

Presentation transcript:

Pixel Chip Testing S. Easo, RAL Current Status of the Pixel Chip Testing. Plans for an LHCb Test Setup at CERN.

Current Status On the IC tester the chip is proved to be functional. This setup is mostly software controlled. The only external hardware needed is the pixel chip glued and bonded on a board and a couple of power supplies. IC tester is in high demand at CERN; Not suitable for high statistics tests. For detailed chip characterization another Test Setup is used: A Test Setup using VME is working in ALICE. This uses different boards which are custom made within the CERN-ALICE group. I am copying this setup and its software for LHCb.

Current Pixel Test Setup JTAG Controller PC VME MXIMXI PILoTPILoT Readout Interface Pixel Chip Board to which the Pixel chip is glued and Bonded. +5V,-5V analogue, +5V digital Power Supplies Fast Controls Data Con- figu- ration

Pixel Test Setup Pilot Board: Provides the Fast Control Signals. Examples: (1) Strobe ( first level trigger) is a signal to write data to the pixel chip FIFOS. (2) Next Event Read is a signal to read data from pixel chip FIFOs. (3) Test_Pulse: To trigger the injection of test charge into pixel preamplifiers. Acquires Data and performs zero suppression. Current version works at 10 MHz. It can be modified to 40 MHz. Readout Interface Board (from Mike Burns): Provides Power, Analogue bias etc. Converts LVDS GTL. Pixel chip uses GTL. Is expected to be replaced by the PIXIE board in the future, for testing the pixel chip on carriers and tubes.

Pixel Test Setup JTAG Controller: Commercially produced board. Used for the slow controls: Setup Thresholds, Configuration etc. ALICE uses a version mounted on the VME crate. I use the PC version since it is the only one available for now. This controller is verified to be functional, during last month. Data path: Pixel Chip-->Readout Interface-->Pilot board-->PC. Readout Software: Labview for now. Can be translated in the future. Example of Measurement: S curve to estimate the noise and threshold of Pixel channels.

Plans and Summary For the LHCb setup, all components except the Readout Interface Board are available. This board is undergoing tests and is expected to be available in a few days. I plan to write the software needed for the characterization of the chips and perform the characterization on the bare chips glued on the board. This setup is expected to be a prototype for LHCb specific tests on the chip. We should be able to use this, to test chips mounted on carriers, tubes etc. Once functional, we can copy this setup for large scale HPD testing.