Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS IP Processing Wrapper Tutorial Gigabitkits Workshop August

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS IP Processing Wrapper Library l Collection of protocol components in VHDL l Module interface for higher protocol levels l Translation from/to cells to/from higher levels l Components handle protocol checksums and CRCs

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Stacked Wrapper

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS The Cell-Processor Checks the HEC and drops erroneous cells Dispatch cells to application or bypass Handles control cells Recomputes HEC for outgoing cells

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS AAL5 Frame Processor Frame Processor detects frame boundaries FP handles CRC FP segments data into cells Frame Detection Cell AAL5CRC ation Segment

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS IP Processor Verify IP version Check Header Checksum for application (ev. Drop) Decrease TTL field (ev. ICMP msg) Signal start of payload (SOP) Recompute Header Checksum IP Detect TTLDec IPProcessor Checksum + Checksum

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS UDP Processor Check for protocol ID (17) Signal start of datagram (SOD) Handle UDP checksum

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Space & Speed Space/LUTsSpeed/MHz Cell Processor Frame Processor IP Processor UDP Processor550114

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Delays Delay for short packagesDelay for long packages InputoutputInputoutput Cell Processor 4646 Frame Processor IP Processor UDP Processor

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Throughput Throughput for short packages Throughput for long packages InputoutputInputoutput Cell Processor 4646 Frame Processor IP Processor UDP Processor

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Downloading the library l Download at l VHDL simulation files l edif files for synthesis l VHDL wrapper files »Combine several layers for convenience

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Cell Wrapper files l Cellprocessor.edn »Synthesized cell processor »Use during place & route of your design l Cellprocessor.vhdl »Structural simulation file »Use during simulation of design

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Frame Wrapper Files l Frameprocessor.edn »Synthesized frame processor »Use during place & route of your design l Frameprocessor.vhdl »Structural simulation file »Use during simulation of design l Framewrapper.vhdl »Combine the frame processor with the cell processor

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS IP Wrapper Files l ipprocessor.edn »Synthesized IP processor »Use during place & route of your design l ipprocessor.vhdl »Structural simulation file »Use during simulation of design l ipwrapper.vhdl »Combine the ip processor with the frame wrapper

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS UDP Wrapper Files l udpprocessor.edn »Synthesized UDP processor »Use during place & route of your design l udpprocessor.vhdl »Structural simulation file »Use during simulation of design l udpwrapper.vhdl »Combine the UDP processor with the IP wrapper

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS UDP Application l Input signals »D_MOD_IN (data input) »DataEn_MOD_IN (data enable) »SOF_MOD_IN (start of frame) »SOD_MOD_IN (start of datagram) »EOF_MOD_IN (end of frame) »TCA_MOD_IN (congestion control) l Output signals »D_OUT_MOD (data output) »DataEn_OUT_MOD (data enable) »SOF_OUT_MOD (start of frame) »SOD_OUT_MOD (start of datagram) »EOF_OUT_MOD (end of frame) »TCA_OUT_MOD (congestion control) l General signals l CLK (clock signal) l Reset_l (synchronous reset, active low)

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Clock & Reset l CLK »Clock signal for module »100 MHz l Reset_l »Synchronous reset »Low for 1 clock cycle to reset state machines »Set by reconfiguration logic

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Data l D_MOD_IN + D_OUT_MOD »Data bus »32 bit wide l DataEn_MOD_IN + DataEn_OUT_MOD »Hi during valid payload data »Hi during trailer words (after EOF)

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Boundary signals l SOF_MOD_IN + SOF_OUT_MOD »Hi for 1 clock cycle during first ATM header word »Signals start of a new AAL5 frame »Note: HEC is not sent after this signal l SOD_MOD_IN + SOD_OUT_MOD »Hi for 1 clock cycle during first word of UDP header »UDP payload starts after two valid payload words (check Data Enable) »Not enabled if not a UDP packet l EOF_MOD_IN + EOF_OUT_MOD »Hi during 1 clock cycle of last payload word of datagram »Followed by the two trailer words of the AAL5 frame

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Congestion Control l TCA_MOD_IN + TCA_OUT_MOD »TCA signal is hi when data can be accepted, lo if no data should be sent »Wrappers back-propagate TCA to the NID »Data in pipeline will still be forwarded (~cell time) »IP wrapper has big packet buffer for outgoing data

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Signals

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Integrate Application UDP Processor Application IP Processor Cell Processor Frame Processor Output Input UDP Wrapper

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Configuration

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Simulation

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS RAD l Application (with wrappers) l Reconfiguration logic (reset and repramming) l Control Cell Processor (if needed for SRAM/SDRAM access) l SRAM/SDRAM controller (if needed) Application Control ReconfigSRAM Interface Control Processor Cell RAD Ingress Port Egress Port Ingress Port SRAM Egress Port

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Synthesis l Add VHDL files for application l Set part to “Xilinx Virtex 1000E fg680” l Synthesize l E.g. Synplicity/Synplify

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Place & Route l Copy wrapper-edif files (*.edn) to target directory l “ngdbuild –p xcv1000e-7-fg680 design –uc design.ucf” l “map –p xcv1000e-7-fg680 –o top.ncd design.ncd design.pcf” l “par –w –ol 2 top.ncd design.ncd design.pcf” l “bitgen design.ncd –b –l –w –f bitgen.ut”

Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS Downloading bitfile to FPX l Connect JTAG cable to FPX l Select bitmap file in JTAG programmer l Program chip l Reset switch (NCHARGE on