Constraint-Based Embedded Program Composition IMPACT Rapid Construction of Efficient Embedded Systems. Multiple System Variants for Little Cost. Rapid, Low Cost System Evolution. Traceabilty from Requirements to Implementation Ability to Customize Tools for Specific Domains New Design Methodology: AO + Model-Based NEW IDEAS AO Merging a Model-Based & Language Approaches Model-Based System Design Space Spec Textual Constraints/Requirements Spec. System-Level Constraint Expression Language AO-Based Strategy Language for Constraint Distribution and Application Weaver Infrastructure for Automated Constraint Application Meta-Weaver for Specification of Weavers Automated Application of RT Constraints SCHEDULE. 3/01 Spec. & Strategy Lang. V1. 6/01 Constraint Weaver & ATR Demo. 3/02 Spec. & Strategy Lang. V2. 9/02 Resource Constr. Weaver/Demo. 3/03 Complete Spec/Strat Lang. 11/03 Meta-Weaver Descr.. 9/04 SW Radio Demo System SW/HW Description Waveform Descr. #1 AO Constraint Specs Constraint Weaver System Composition Waveform Descr. #N Constraint Weaver System Composition System Design Space/ Embedded Object Specification Customized/Optimized Embedded System SW-Based Radio

Institute for Software Integrated Systems Vanderbilt University Constraint-Based Embedded Program Composition Institute for Software Integrated Systems Vanderbilt University PI: Ted Bapty Jeff Gray, Sandeep Neema

Project Goals Investigate the Interactions between MBS+AO Extend Existing Model-Based Embedded System Design System –Language-based Constraints, –Strategy Language for Constraint Distribution Customize the tools for Communications Demonstrate on Software-Based Radio Application

Reconfigurable Runtime Environment Adaptive Computing Systems Model-Integrated Design Environment Behavioral Models MODELS Graphical Model Builder Model Analysis Tools Algorithm Models Resource Models ATR SW HW SW HW Simulation Environment System Generation Multi-Aspect Modeling Environment

Model-Integrated Design Environment (MIDE) Design Capture for HW/SW Codesign: Multiple Aspects –Software/Algorithm Data Flow with Multiple Design Alternatives –Hardware Resources: Heterogeneous (DSP,RISC,FPGA) –Dynamic System Behavior: Multi-modal systems –Constraint Specification Language: Link SW/HW/Behavior –Result: Comprehensive, Flexible HW/SW System Model Analysis of Models (Design) –Design-Space Exploration: Optimize design, select best configurations from alternative designs Highly scalable using OBDD –Numerical/Algorithmic Simulation with Matlab –Multiple-Resolution Performance Simulation with Discrete Event Simulator

Model-Integrated Design Environment (MIDE) HW/SW System Synthesis –Generate Real-Time Schedules –Generate VHDL for FPGA or ASIC –Generate Interconnection Topology/Communication Maps –Generate Reconfiguration Manager Configuration –Result: Functional HW/SW System w/ Dynamic Reconfiguration Capabilities. Compatible with Industry-standard VHDL Compilers Runtime Support –Microkernel for Heterogeneous Distributed DSP’s –Virtual Hardware Microkernel for FPGA/ASIC –Dynamic System Reconfiguration Controller –Real-Time, reconfiguration support. –Result: Portable, heterogeneous uniform execution environment

Multiple-View Graphical Modeling/ Flexible Design Space Behavioral Structural Resource

Modeling Paradigm Structural/Algorithmic Description Compound Software Hardware Compound Primitive Template Primitive Template Compound Primitive Compound Primitive Compound Model/Object HierarchyExample Model Primitive

Defining A Design Space Templates for Algorithm Alternatives Long Range Track Algorithm Alternatives PreprocessFilter XCorr Error Comp Image DB Spatial Domain Preprocess2D FFT Mult Error Comp Img Spec DB Spectral Domain Sensor Guidance Loss of Track

Modeling Paradigm Resource Models Processor Network Ports ASIC CorePortsCore FPGA Ports Object Hierarchy Example Model Network Processor FPGA ASIC

Modeling Paradigm Behavioral Description: Hierarchical State Machine Mode A Mode B Mode C Attributes Algorithms Performance Specs Constraints (Power/Size/User Defined) Transition Rules Transition Rules Transition Rules Transition Rules

S1S3S2 hierarchical parallel FSM Behavior Model Processing Structure Models Behavior and Compatibility Constraints P1 P3 P2 e1[S21]/ / /../ Pr2 Pr1 Pr3 C1 Resource Models Resource Constraints hierarchical interconnect alternatives (mode=(S1 or S2))implies(P1=P1 i )) (mode!=S3)implies (Pr2.assignees =(P1 i or P2 j ))and(Pr2=Pr2 j ) (D1.time - D2.time) < 2 Timing Constraints Constraint Modeling Power Constraints (mode=S2 implies (Proc.Powr<10))

Design Space Exploration Behavior Mod. (Hier. Par. FSM) Structural Mod. (Hier. Altern.) Constraints (OCL) Binary Encoding Binary Encoding Binary Encoding BDD Representation BDD Representation BDD Representation Full Symbolic Design Space Pruned Design Space Resource Model Binary Encoding BDD Representation OBDD Analysis

System Synthesis Kernel BIDIR IFC XC4010 FPGA C40 DSP Altera FPGA DATA I/O HOST PC STREAMS IFC - BIDIR STREAMS IFC OUT STREAMS IFC IN IN IFC OUT IFC P2 P1 OUT IFCIN IFC P2 P3 IN IFCOUT IFC ASIC IFC P3 P2 Multiple Data Streams P1 ASIC Real-Time Schedules, Communication Maps VHDL for FPGA Configs I/O Interfaces I/O Interfaces COMM Interfaces

Difficulties in Managing Graphically Specified Constraints A B cde 12 3 B cde 1’’2’’ 4 F B cde 1’2’ 3’ 4 Multiple Levels of Hierarchy Replicated Structures Context Sensitive Change Maintenance???

Constraints Are Critical!! Define functional properties of system Ensure proper component interaction Designer’s leverage to guide synthesis Bad Constraint Management = Inflexible, unwieldy development.

Develop Constraint Language

Aspect-Oriented Constraint Language Develop Language for Specifying Constraints –Operational Mode-dependent behavior –Performance Timing Cost: Power/Parts $/Volume/Weight –Composibility: (Part A ~ Part B, Part C !~ Part D) –Resource: Process X requires Part D –Relationships to Modeling Aspects

Constraint Application Strategy Language Specify how to apply constraints across object hierarchy. Determines how constraints are divided/responsibility shared among components. Flexible to permit different goals –Latency optimization –Throughput optimization –….

Demonstration Plans SW “RF” Components Runtime Infrastructure Synthesis Waveform #1 Waveform #2 Weaver Unconstrained SW Radio Real-Time Design Strategy