Interfaces to External EDA Tools Debussy Denali SWIFT™ Course 12

All materials updated on: September 30, 2004 Outline 1.Debussy Debugging System 2.Denali Memory Models 3.SWIFT SmartModels Library

All materials updated on: September 30, Debussy Debussy is a debugging system developed by Novas Software. Active-HDL can work with Debussy in two modes: Post-processing Mode In the Post-processing Mode, the simulation and debugging are two separate stages. First, Active-HDL is used to simulate the design. During the simulation Active-HDL, dumps the required data to a Fast Signal Database (FSDB). Once the simulation process is over, the design can be loaded into Debussy. Debussy will read the signal history from the FSDB database created by Active-HDL. Dumping data to the FSDB database can be controlled either directly from HDL source code or with macro commands and FSDB PLI tasks. The commands and the PLI tasks can be placed in macro files or issued interactively from the Console window. Interactive Mode In the Interactive Mode, Active-HDL acts as a slave application for Debussy and can be controlled directly from the Debussy GUI. Debussy sends commands to Active-HDL and reads simulation data from it. Using the Interactive Mode requires some initial setup, such as compiling the project in Active-HDL, adding a PLI application and preparing the debussy.rc file (templates are available).

All materials updated on: September 30, a Debussy & Active-HDL in post-processing mode Dumping FSDB databases can be controlled either directly from VHDL source code or with macro commands. To dump FSDB databases directly from VHDL code, declare the aldec library and use the package fsdb_wrapper: library aldec; use aldec.fsdb_wrapper.all; Debussy FSDB procedures (tasks) can be placed inside any process, FSDB_DUMP: process begin fsdbDumpfile("simdata.fsdb"); fsdbDumpvars(0, ""); wait; end process;

All materials updated on: September 30, b Debussy & Active-HDL in post-processing mode If you do not want to modify your VHDL source code, you can dump FSDB databases using macro commands. The commands can be placed in macros or typed in the Console window after initializing the simulation process. asim testbench fsdbDumpfile("simdata.fsdb") fsdbDumpvars(0, "") run -all Simulation data is automatically flushed to the FSDB database when simulation is finished with the endsim command.

All materials updated on: September 30, c Debussy & Active-HDL Sample Design Open Design “DebussyPostMode” Run macro runme.do

All materials updated on: September 30, d Debussy & Active-HDL Sample Design Step #1 : Compilation. Step #2 : Simulation Initialization. Step #3 : Invoking FSDB Tasks. Step #4 : Running Simulation. Step #5 : End Simulation. Step #6 : Running Debussy. Step #7 : Creating Waveform.

All materials updated on: September 30, e Debussy & Active-HDL Sample Design Choosing FSDB File. Choosing signals.

All materials updated on: September 30, f Debussy & Active-HDL Sample Design Debussy & Active-HDL Waveforms

All materials updated on: September 30, Denali Active-HDL supports memory models distributed by the Denali software. Denali models can be instantiated in Verilog designs only. Memory models communicate with Active-HDL via a PLI library. The PLI library must be built by the user. PLI tasks to control memory models can be placed directly in the Verilog code or called directly from the Console window. To display the PureView memory viewer after initializing the simulation process, type $mmstartpureview in Console.

All materials updated on: September 30, a Denali Sample Design Obtaining memory description file Step #1: Obtain SOMA file with description of SRAM memory IDT memory model description files are available at eMemory.com.

All materials updated on: September 30, b Denali Sample Design Creating Verilog source Step #2 : Launch Denali PureView and open SOMA file.

All materials updated on: September 30, c Denali Sample Design Creating Verilog source Step #3 : Configure parameters for the memory model.

All materials updated on: September 30, d Denali Sample Design Creating Verilog source Step #4 : Generate Verilog wrapper file for memory model. - First, specify the Simulation Environment in Options menu. Select NC Verilog from the list.

All materials updated on: September 30, e Denali Sample Design Verilog source A ready-to-use Verilog file will be generated. Use Save Source As from the File menu to save the file at desired lacation. NOTE: In order to use Denali PureView for debugging purposes, the initial block has to be modified as follows: initial begin $mmtcleval("mmsimulationdatabase simdb_filename"); $sram_access(a,webar,csbar,oebar,bebar,io,den_io); end

All materials updated on: September 30, f Denali Sample Design Adding HDL file to design Step #6 : Add the source file to the Design and compile it. Memory models communicate with Active-HDL via PLI library. This library (Denali.dll) has to be built by the user. Detailed instructions are provided in Active-HDL On-line Help in section Active-HDL Interfaces | Denali Interface | Building the Denali Library. Neccessary files can be found in Denali subfolder of Active-HDL installation directory. Once the Denali.dll library is built, it has to be added to Verilog PLI applications tab of Design Settings

All materials updated on: September 30, g Denali Sample Design Initializing simulation Step #7 : After simulation initialization memory interface is accessible.

All materials updated on: September 30, h Denali Sample Design Writing data to memory Step #8 : We can prepare stimulators and write data to memory. Step #9 : We can also see the contents of memory by using $mmstartpureview task

All materials updated on: September 30, i Denali Sample Design Choosing memory to view Step #10 : After choosing memory instance we will see memory contents …

All materials updated on: September 30, j Denali Sample Design Memory view in Denali “PureView”

All materials updated on: September 30, SWIFT The SWIFT TM SmartModels Library is an external library containing the behavioral simulation models of the standard integrated circuits. The range and complexity of models varies and starts from simple TTL devices, such as gates, and ends with complex VLSI structures, such as microprocessors and high-density programmable logic. Active-HDL provides an interface that allows customers to use these models within the Active-HDL environment The SmartModels Library's software (swift.dll) is required to use SmartModels in Active-HDL The inclusion of SmartModels Libraries allows users to target Virtex- II Pro devices as well (fully supports PowerPC and Rocket I/O)

All materials updated on: September 30, a SWIFT & Active-HDL Sample Design Install SmartModel library ‘i27256’ Open SwiftModel design Open runme.do macro and execute it We are going to simulate model “i27256” in Active- HDL …

All materials updated on: September 30, b SWIFT Sample Design Creating foreign architecture To use SmartModels in Active-HDL's VHDL-based designs, the communication between an external library and the Active-HDL environment has to be established. It can be done by using the library's interface (swift.dll). Additionally, Active-HDL provides a program that allows users to create a code containing the foreign entity/architecture pair associated with the SmartModels library. Then, such a code can be compiled and used in your design. Active-HDL's sm_prepare creates entity/foreign architecture pairs for SmartModels automatically.

All materials updated on: September 30, c SWIFT Sample Design Compilation & Simulation

All materials updated on: September 30, d SWIFT & Active-HDL Command Channel The command channel is a SmartModel feature that allows the user to invoke SmartModel specific commands. The interface built-in to the Active-HDL environment allows customers to use two kinds of commands : Model Commands & Session Commands