1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison.

Slides:

Advertisements

Similar presentations

© 2013 IBM Corporation Use of Hierarchical Design Methodologies in Global Infrastructure of the POWER7+ Processor Brian Veraa Ryan Nett.

Advertisements

Wires.

Keeping Hot Chips Cool Ruchir Puri, Leon Stok, Subhrajit Bhattacharya IBM T.J. Watson Research Center Yorktown Heights, NY Circuits R-US.

THE RAW MICROPROCESSOR: A COMPUTATIONAL FABRIC FOR SOFTWARE CIRCUITS AND GENERAL- PURPOSE PROGRAMS Taylor, M.B.; Kim, J.; Miller, J.; Wentzlaff, D.; Ghodrat,

Improving Placement under the Constant Delay Model Kolja Sulimma 1, Ingmar Neumann 1, Lukas Van Ginneken 2, Wolfgang Kunz 1 1 EE and IT Department University.

Digital Integrated Circuits© Prentice Hall 1995 Interconnect COPING WITH INTERCONNECT.

CS 7810 Lecture 12 Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors D. Brooks et al. IEEE Micro, Nov/Dec.

SoC Interconnect Modeling Venkata Krishna N. Dhulipala 11/20/2008.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 14: Interconnects Prof. Sherief Reda Division of Engineering, Brown University.

Lecture #25a OUTLINE Interconnect modeling

EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 0.1 Process: Focus on Change Challenges & Directions Technology Paradigm Shifts Market Segment Semiconductor.

Ryan Kastner ASIC/SOC, September Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer.

Temperature-Aware Design Presented by Mehul Shah 4/29/04.

6.893: Advanced VLSI Computer Architecture, September 28, 2000, Lecture 4, Slide 1. © Krste Asanovic Krste Asanovic

On-Chip Communication Architectures

TLC: Transmission Line Caches Brad Beckmann David Wood Multifacet Project University of Wisconsin-Madison 12/3/03.

EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today.

Power Reduction for FPGA using Multiple Vdd/Vth

Research on Analysis and Physical Synthesis Chung-Kuan Cheng CSE Department UC San Diego

Are classical design flows suitable below 0.18  ? ISPD 2001 NEC Electronics Inc. WR0999.ppt-1 Wolfgang Roethig Senior Engineering Manager EDA R&D Group.

CSE477 L01 Introduction.1Irwin&Vijay, PSU, 2002 ECE484 VLSI Digital Circuits Fall 2014 Lecture 01: Introduction Adapted from slides provided by Mary Jane.

Lecture 12 Review and Sample Exam Questions Professor Lei He EE 201A, Spring 2004

CAD for Physical Design of VLSI Circuits

ASIC Design Flow – An Overview Ing. Pullini Antonio

Logic Synthesis for Low Power(CHAPTER 6) 6.1 Introduction 6.2 Power Estimation Techniques 6.3 Power Minimization Techniques 6.4 Summary.

ECE Advanced Digital Systems Design Lecture 12 – Timing Analysis Capt Michael Tanner Room 2F46A HQ U.S. Air Force Academy I n t e g r i.

HDL-Based Layout Synthesis Methodologies Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {

Digital Integrated Circuits© Prentice Hall 1995 Interconnect COPING WITH INTERCONNECT.

1 L24:Crosstalk-Concerned Physical Design Jun Dong Cho Sungkyunkwan Univ. Dept. ECE Homepage : vada.skku.ac.kr.

Washington State University

CSE 494: Electronic Design Automation Lecture 2 VLSI Design, Physical Design Automation, Design Styles.

Massachusetts Institute of Technology 1 L14 – Physical Design Spring 2007 Ajay Joshi.

EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Interconnect Jan M. Rabaey Anantha Chandrakasan Borivoje.

EE415 VLSI Design 1 The Wire [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Wire Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

ASIC, Customer-Owned Tooling, and Processor Design Nancy Nettleton Manager, VLSI ASIC Device Engineering April 2000 Design Style Myths That Lead EDA Astray.

NUMERICAL TECHNOLOGIES, INC. Assessing Technology tradeoffs for 65nm logic circuits D Pramanik, M Cote, K Beaudette Numerical Technologies Inc Valery Axelrad.

CSE 242A Integrated Circuit Layout Automation Lecture 1: Introduction Winter 2009 Chung-Kuan Cheng.

Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY.

INTERCONNECT MODELING M.Arvind 2nd M.E Microelectronics

1 Interconnect/Via. 2 Delay of Devices and Interconnect.

Lecture 14: Wires. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 14: Wires2 Outline  Introduction  Interconnect Modeling –Wire Resistance –Wire Capacitance.

Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect. n Switch logic.

Distributed Computation: Circuit Simulation CK Cheng UC San Diego

VLSI INTERCONNECTS IN VLSI DESIGN - PROF. RAKESH K. JHA

By Nasir Mahmood.  The NoC solution brings a networking method to on-chip communication.

Trends in IC technology and design J. Christiansen CERN - EP/MIC

Interconnect/Via.

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect.

A High-Speed & High-Capacity Single-Chip Copper Crossbar John Damiano, Bruce Duewer, Alan Glaser, Toby Schaffer, John Wilson, and Paul Franzon North Carolina.

A Design Flow for Optimal Circuit Design Using Resource and Timing Estimation Farnaz Gharibian and Kenneth B. Kent {f.gharibian, unb.ca Faculty.

EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles Zhiyi Yu, Bevan Baas VLSI Computation Lab, ECE Department University of California,

CS203 – Advanced Computer Architecture

14/2/20041 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation® Technion - Israel Institute.

1 Design and Implementation of the POWER5 Microprocessor J. Clabes 1, J. Friedrich 1, M. Sweet 1, J DiLullo 1, S. Chu 1, D. Plass 2, J. Dawson 2, P. Muench.

Introduction to ASICs ASIC - Application Specific Integrated Circuit

Power-Optimal Pipelining in Deep Submicron Technology

CS203 – Advanced Computer Architecture

The Interconnect Delay Bottleneck.

Crosstalk If both a wire and its neighbor are switching at the same time, the direction of the switching affects the amount of charge to be delivered and.

Circuits and Interconnects In Aggressively Scaled CMOS

Topics Driving long wires..

Jason Cong, David Zhigang Pan & Prasanna V. Srinivas

An Illustration of 0.1µm CMOS layout design on PC

An Automated Design Flow for 3D Microarchitecture Evaluation

Circuit Characterization and Performance Estimation

COPING WITH INTERCONNECT

Reading (Rabaey et al.): Sections 3.5, 5.6

Jason Cong, David Zhigang Pan & Prasanna V. Srinivas

Presentation transcript:

1 ECE 556 Design Automation of Digital Systems By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison

2 Outline ä Microprocessor Technology Trends and Design Issues ä Interconnect delay trends ä Circuit type trends ä Research summary

3 Microprocessor Design Challenges ä High performance ( > 500 Mhz) ä Low cost (< $100) ä Low power consumption (< 10W mobile) ä More functionality (KNI MMX) ä Shorter time to market (< 18 months) ä Satisfies different market segments (server, sub- $1000) ä Competition ä …. Mission Impossible!

4 Tentative Class Schedule ä Technology Trends (1 class) ä Interconnect Modeling and Optimization: (1 week) ä basic routing: maze-routing ä wire-sizing, buffer-sizing, buffer-insertion ä Introduction to Verilog (1 week) ä Linear programming and Introduction to C and C++ language (1 week) ä Routing: (2 week) ä Clock routing (0.6 week) ä Global and channel routing, Tree routing (1.4 week) ä Timing Analysis (1 week) ä Delay Characterization, Power Characterization ä PERL and Latch based timing analysis ä Partitioning and Placement (1.5 week) ä Floorplanning (1 week)

5 Deal With It! ä Higher clock frequencies ä New processes: 0.18 micron, copper ä Architecture level ä Superscalar, super-pipeline, out-of-order execution, speculative execution, EPIC, VLIW, ILP, multi-thread ä Circuit level ä Aggressive dynamic circuits synthesis ä Sizing, parallel re-powering, logic minimization ä Physical Design ä Performance-driven place and route, floorplaning ä Wire-sizing, buffer-sizing, buffer-insertion

6

7

8

9

10

11

12 Size of Team Explodes

13

14 Process Overview ä New process (0.18 um) ä High aspect ratio ä Low sheet rho (resistance)  Low-  dielectric (capacitance) (3.55 vs. 4.10) ä Good Electromigration property ä 6 metal layers ä M1 tight pitch for density (X-cap) ä M2-M3 middle pitch for density & performance (X-cap) ä M4-M6 high pitch (low resistance) for performance (Inductance) ä Future ä Copper - Less resistance more inductance effect ä SOI - the M1 coupling strange

Micron, 5 Layer Technology IEDM 96

16 M6 M5 M4 M3 M2 M Micron, 6 Layer Technology IEDM 99

17 Gate Delay.v.s. Scaling IEDM 99

18 Interconnect Resistance Grows Super Linearly IEDM 99

19 Interconnect Delay Trend IEDM 99

20

21

22

23 Interconnect Complicated Design Flow Architecture RTL Logic Gate Layout Over tens of iterations!

24 Signal Integrity A new design challenge CrossCap 1 2 Crosstalk

25 Inductance effect emerging ä An old clock tree ä Freq domain up to 1Ghz ä PVL and PRIMA with order 16 find the exact ä A newer ckt, a section of power grid ä Has L’s ä PVL and PRIMA with 60th order ä Frequencies more than 0.6 Ghz are not covered Frequency (Ghz)

Multi-Point PRIMA-34 PRIMA-80 TIM PVL-80 Some MOR result

27

28

29 Model order reduction ä We need efficient tools to analyze the interconnect dominant circuits (power grids, packages etc.) accurately in a reasonable amount of time  Promising Model Order Reduction (MOR) techniques Nonlinear Elements Linear Elements Nonlinear Elements Reduced Model

30 Power Consumption  P  C V 2 f, where ä C = Capacitance ~ Area ä V = Supply Voltage ä f = Operation Frequency

31 Power Trend

32 Supply Voltage Trends

33 Deal With It! ä Interconnect ä Wire- and Repeater- Sizing ä Repeater Insertion ä Performance-driven noise-aware routing ä New material: Low resistance (Cooper), Low k material (SiN2) ä Gates ä Gate Sizing ä New Circuit Exploration - Dynamic Circuit, Dual Vt ä ….

34 Standby Power Trend

35 Threshold Voltage v.s. Supply Voltage

36 Vt v.s. Delay

37 Dual Vt circuit High Vt Low Vt

38 Aggressive circuit styles

39 Clock delayed and Self-resetting dynamic circuits

40 Process limitations