Penn ESE370 Fall Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 14: October 1, 2014 Layout and Area Midterm 1 Average: 79.7 (of 85) Std. Dev.: 4.4

Problem 4 Failure – my fault –Should be: min(max(3*(Va-Vb),0),1) Failed to provide good diagnosis of restoration understanding –Noisy measurement Result –Exam not provide very high precision assessment of students Cannot distinguish A from B students Penn ESE370 Fall Townley & DeHon

Exam Successes (not fail) Does provide enough information to diagnose anyone ein big trouble and should drop –separate the DF from AB Diagnose a few R C items –Need that down cold  will use heavily Did focus you on understanding these items, including restoration Penn ESE370 Fall Townley & DeHon

4 Today Layout –Transistors –Gates Design rules Standard cells Penn ESE370 Fall Townley & DeHon

Layout Penn ESE370 Fall Townley & DeHon

6 Transistor Side view Perspective view Penn ESE370 Fall Townley & DeHon

7 Layout Sizing & positioning of transistors Designer controls W,L t ox fixed for process –Sometimes thick/thin oxide “flavors” Penn ESE370 Fall Townley & DeHon

8 NMOS Geometry Top viewPerspective view L W Penn ESE370 Fall Townley & DeHon

9 NMOS Geometry Top view L W Color scheme –Red: gate –Green: source and drain areas (n type diffusion) SDG Penn ESE370 Fall Townley & DeHon

10 NMOS vs PMOS Rabaey text, Fig 2.1 Penn ESE370 Fall Townley & DeHon NMOS built on p substrate PMOS built on n substrate –Needs an N-well

11 PMOS Geometry n well L W Color scheme –Red: gate –Orange: source and drain areas (p type) –Green: n well NMOS built on p wafer –Must add n material to build PMOS SDG Penn ESE370 Fall Townley & DeHon

12 Body Contact “Fourth terminal” Needed to set voltage around device –PMOS: V b = V dd –NMOS: V b = GND At right: PMOS (orange) with body contact (dark green) Penn ESE370 Fall Townley & DeHon

13 Body Contact Needed to set voltage around device –PMOS: V b = V dd –NMOS: V b = GND What happens if NMOS body contact is V dd ? Penn ESE370 Fall Townley & DeHon

14 Body Contact Needed to set voltage around device –PMOS: V b = V dd –NMOS: V b = GND What happens if NMOS body contact is V dd ? –Polarity of field wrong –Won’t invert channel Penn ESE370 Fall Townley & DeHon

15 Body Contact Needed to set voltage around device –PMOS: V b = V dd –NMOS: V b = GND Always to same supply as the transistor might be connected in CMOS Penn ESE370 Fall Townley & DeHon

Rotate All but PMOS Transistor 90 degrees

17 Interconnect Connect transistors –Different layers of metal “Contact” - metal to transistor “Via” - metal to metal Penn ESE370 Fall Townley & DeHon

18 Interconnect Connect transistors –Different layers of metal “Contact” - metal to transistor “Via” - metal to metal Penn ESE370 Fall Townley & DeHon

19 Interconnect Cross Section ITRS 2007 Penn ESE370 Fall Townley & DeHon

20 Masks Define areas want to see in layer –Think of “stencil” for material deposition Use photoresist (PR) to form the “stencil” –Expose PR through mask –PR dissolves in exposed area –Material is deposited Only “sticks” in area w/ dissolved PR Penn ESE370 Fall Townley & DeHon

21 Masking Process Goal: draw a shape on the substrate –Simplest example: draw a rectangle Silicon wafer Mask Penn ESE370 Fall Townley & DeHon

22 Masking Process First: deposit photoresist photoresist Mask Silicon wafer Penn ESE370 Fall Townley & DeHon

23 Masking Process Expose through mask –UV light Penn ESE370 Fall Townley & DeHon

24 Masking Process Remove mask and develop PR –Exposed area dissolves –This is “positive photoresist” Penn ESE370 Fall Townley & DeHon

25 Masking Process Deposit metal through PR window –Then dissolve remaining PR Why not just use mask? –Masks are expensive –Shine light through mask to etch PR –Can reuse mask Penn ESE370 Fall Townley & DeHon

26 Reverse Engineer Inverter Layout Penn ESE370 Fall Townley & DeHon

27 Layout Revisited How to “decode” circuit from layout? Penn ESE370 Fall Townley & DeHon

28 Reverse Engineer Inverter Layout Penn ESE370 Fall Townley & DeHon Power (Vdd) GND

29 Reverse Engineer Inverter Layout Where is PMOS transistor? NMOS? Penn ESE370 Fall Townley & DeHon Power (Vdd) GND

Penn ESE370 Fall DeHon 30 Layout to Circuit 1. Identify transistors Penn ESE370 Fall Townley & DeHon

31 Inverter Layout Where is Input? Penn ESE370 Fall Townley & DeHon

32 Inverter Layout Where is Output? Penn ESE370 Fall Townley & DeHon

33 Layout to Circuit 2. Add wires Penn ESE370 Fall Townley & DeHon

34 Layout to Circuit 2. Add wires Penn ESE370 Fall Townley (DeHon)Penn ESE370 Fall Townley & DeHon

35 Inverter Layout What is structure at top and bottom? Penn ESE370 Fall Townley & DeHon

36 Layout to Circuit 2. Add wires Penn ESE370 Fall Townley (DeHon)Penn ESE370 Fall Townley & DeHon

37 Layout to Circuit 2. Add wires Penn ESE370 Fall Townley (DeHon)Penn ESE370 Fall Townley & DeHon

38 Design Rules Why not adjacent transistors? –Plenty of empty space –If area is money, pack in as much as possible Recall: processing imprecise –Margin of error for process variation Penn ESE370 Fall Townley & DeHon

39 Design Rules Contract between process engineer & designer –Minimum width/spacing –Can be (often are) process specific Lambda rules: scalable design rules –In terms of = 0.5 L min (L drawn ) –Can migrate designs from similar process –Limited scope: 22nm process != 1  m Penn ESE370 Fall Townley & DeHon

Design Rules: Some Examples Penn ESE370 Fall Townley & DeHon n doping p doping gate contact metal 1 metal 2 via Legend

41 Layout #2 (practice) Penn ESE370 Fall Townley & DeHon

42 Layout #2 (practice) How many transistors? –PMOS? –NMOS? How connected? –PMOS, NMOS? Inputs connected? Outputs? What is it? Penn ESE370 Fall Townley & DeHon

43 Standard Cells Lay out gates so that heights match –Rows of adjacent cells –Standardized sizes Motivation: automated place and route –EDA tools convert HDL to layout Penn ESE370 Fall Townley & DeHon

Standard Cell Area invnand3 All cells uniform height Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die

Standard Cell Layout Example Penn ESE370 Fall Townley & DeHon

ALU in Standard Cell Penn ESE370 Fall Townley & DeHon gchen.gif

Penn ESE370 Fall Townley & DeHon Standard Cell Area invnand3 All cells uniform height Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die

48 Big Idea Layouts are physical realization of circuit –Geometry tradeoff Can decrease spacing at the cost of yield Design rules Can go from circuit to layout or layout to circuit by inspection Penn ESE370 Fall Townley & DeHon

Admin HW5 out –Due Tuesday –(Thursday next week is Fall Break) Here on Friday Penn ESE370 Fall Townley & DeHon