Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 10 Input/Output Organization.

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Presentation transcript:

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 10 Input/Output Organization

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline Asynchronous data transfersAsynchronous data transfers Programmed I/OProgrammed I/O InterruptsInterrupts Direct Memory AccessDirect Memory Access I/O ProcessorsI/O Processors Serial CommunicationSerial Communication Serial Communication StandardsSerial Communication Standards

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Data Transfers

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Transfer

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Source-initiated Data Transfer with Handshaking

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Destination-initiated Data Transfer with Handshaking

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Programmed I/O

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

Example

Example

Example

Example

New Instructions

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New Control Signals IO differentiates I/O and memory accessesIO differentiates I/O and memory accesses –IO = 1 for I/O access –IO = 0 for memory access

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 New States and RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section Modify ALUModify ALU

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section Modify ALUModify ALU Modify control unit (hard-wired)Modify control unit (hard-wired)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section Modify ALUModify ALU Modify control unit (hard-wired)Modify control unit (hard-wired) Register and ALU sections unchangedRegister and ALU sections unchanged

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications Modify register sectionModify register section Modify ALUModify ALU Modify control unit (hard-wired)Modify control unit (hard-wired) Register and ALU sections unchangedRegister and ALU sections unchanged One new micro-operation: DR  Input PortOne new micro-operation: DR  Input Port

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC and CLR signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - INC and CLR signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Unit Changes - Memory Read Signal Memory Read = READ ^ IO’Memory Read = READ ^ IO’

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts PollingPolling

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupts IRQ - Interrupt RequestIRQ - Interrupt Request IACK - Interrupt AcknowledgeIACK - Interrupt Acknowledge

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts ExternalExternal

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts ExternalExternal InternalInternal

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Interrupts ExternalExternal InternalInternal SoftwareSoftware

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Do nothing (until the current instruction has been executed)Do nothing (until the current instruction has been executed)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Do nothing (until the current instruction has been executed)Do nothing (until the current instruction has been executed) Get handler address (vectored)Get handler address (vectored)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Processing Interrupts Do nothing (until the current instruction has been executed)Do nothing (until the current instruction has been executed) Get handler address (vectored)Get handler address (vectored) Invoke handler routineInvoke handler routine

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Vectored Interrupt Hardware

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Non-vectored Interrupt Hardware

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiple Non-vectored Interrupts

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Daisy Chaining

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 IACK in and IACK out

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Parallel Priority Interrupts

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Interrupt States

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Direct Memory Access

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Controller

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes Block/Burst ModeBlock/Burst Mode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes Block/Burst ModeBlock/Burst Mode Cycle Stealing ModeCycle Stealing Mode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 DMA Transfer Modes Block/Burst ModeBlock/Burst Mode Cycle Stealing ModeCycle Stealing Mode Transparent ModeTransparent Mode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- operations

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications - Micro- operations

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 CPU Modifications

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations Block transfer commandsBlock transfer commands

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations Block transfer commandsBlock transfer commands ALU operationsALU operations

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Processors - operations Block transfer commandsBlock transfer commands ALU operationsALU operations Control commandsControl commands

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate) start bitstart bit

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate) start bitstart bit parity bitparity bit

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate) start bitstart bit parity bitparity bit stop bit(s)stop bit(s)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate) start bitstart bit parity bitparity bit stop bit(s)stop bit(s) bit timebit time

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Asynchronous Serial Communication

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Synchronous Serial Communication - HDLC

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Asynchronous Receiver/Transmitters

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 UART Internal Configuration

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Request To SendRequest To Send Clear To SendClear To Send Transmission DataTransmission Data Data Terminal ReadyData Terminal Ready Data Set ReadyData Set Ready Received DataReceived Data Data Carrier DetectData Carrier Detect Ring IndicatorRing Indicator GroundGround RS 232C Standard - Signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection Use RTS, CTS, DTR, and DSR to verify that both devices are activeUse RTS, CTS, DTR, and DSR to verify that both devices are active

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection Use RTS, CTS, DTR, and DSR to verify that both devices are activeUse RTS, CTS, DTR, and DSR to verify that both devices are active Use RI to indicate call statusUse RI to indicate call status

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection Use RTS, CTS, DTR, and DSR to verify that both devices are activeUse RTS, CTS, DTR, and DSR to verify that both devices are active Use RI to indicate call statusUse RI to indicate call status Use DCD to establish connectivityUse DCD to establish connectivity

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 232C Standard - Connection Use RTS, CTS, DTR, and DSR to verify that both devices are activeUse RTS, CTS, DTR, and DSR to verify that both devices are active Use RI to indicate call statusUse RI to indicate call status Use DCD to establish connectivityUse DCD to establish connectivity Use TD and RD to transfer data, and RTS and CTS to coordinate transfersUse TD and RD to transfer data, and RTS and CTS to coordinate transfers

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RS 422 Standard - Signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard Connects one port to several devicesConnects one port to several devices

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Universal Serial Bus Standard Connects one port to several devicesConnects one port to several devices Transfers data in packetsTransfers data in packets –Token packets –Data packets –Handshake packets –Special Packets

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 USB Packet Formats

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary Asynchronous data transfersAsynchronous data transfers Programmed I/OProgrammed I/O InterruptsInterrupts Direct Memory AccessDirect Memory Access I/O ProcessorsI/O Processors Serial CommunicationSerial Communication Serial Communication StandardsSerial Communication Standards