EE/CS 480 Fall September, 2007 University of Portland School of Engineering Project Puffins Complex Multivariable Keypad Input Chip Team RuthAnn Gobble Jordan Way Jonathan Wong Advisor Dr. Aziz Inan, Dr. Peter Osterberg Industry Representative Mr. Wes Mickanin

EE/CS 480 Fall September, 2007 University of Portland School of Engineering Overview Introduction Scorecard Additional Accomplishments Plans Issues/Concerns Conclusions

EE/CS 480 Fall September, 2007 University of Portland School of Engineering Project Puffin will increase security of PIN input devices by exponentially increasing the number of possible PIN combinations. This is done through its use of chorded, synchronous inputs. This will benefit users of ATM’s and other Point of Sale (POS) devices by improving security while increasing pin combinations. Introduction

EE/CS 480 Fall September, 2007 University of Portland School of Engineering Scorecard Previous month’s plans –Define project –Compile team schedule –Complete pre-approval document –Create Functional Specifications –Set up Web Page Shortcomings –Specific MOSIS specifications for Functional Spec. Temperature, max. Current, etc.

EE/CS 480 Fall September, 2007 University of Portland School of Engineering Additional Accomplishments Small scale design built in B2logic –Memory component (PIN storage) –Comparator

EE/CS 480 Fall September, 2007 University of Portland School of Engineering Plans List your team’s plans for next month –Complete version 1.0 of Functional Specs –Have design functional in B2logic –Incorporate possible additions to design Card Reader Auto-lock after x number of incorrect attempts –Complete Project Plan 0.9

EE/CS 480 Fall September, 2007 University of Portland School of Engineering Milestones NumberDescriptionOriginal 8/28/07 Previous 8/28/07 Present 9/25/07 1Project Approval9/11/07 2Functional Spec 1.010/05/07 3Project Plan 1.011/09/07 4Funding Approval11/09/07 5Design Review11/30/07

EE/CS 480 Fall September, 2007 University of Portland School of Engineering Concerns/Issues Complications in design syntax with B2Logic –Human error –Large scale integration on single clock Solutions –See Dr. Osterberg –CPLD and debugging

EE/CS 480 Fall September, 2007 University of Portland School of Engineering Conclusion Introduction Scorecard Additional Accomplishments Plans Issues/Concerns Conclusion