FEE2006, Perugia Simultaneous Photon Counting and Charge Integrating Readout Electronics for X-ray Imaging Hans Krüger, University of Bonn, Germany University of Bonn: Michael Karagounis, Manuel Koch, Edgar Kraft, Hans Krüger, Norbert Wermes University of Mannheim: Peter Fischer, Ivan Peric Philips Research Laboratories Aachen: Christoph Herrmann, Augusto Nascetti, Michael Overdick, Walter Rütten

FEE2006, Perugia Hans Krüger, University of Bonn 1  Photon counting limited to count rates < 10 MHz / pixel Quantum limited noise statistics  Charge integration High photon flux does not reach quantum limited resolution at low photon flux Motivation photon counterintegratorsim. counting and integrating (CIX) # photonsyesnoyes total energynoyes low fluxyesnoyes high fluxnoyes spectral information no yes (mean photon energy)

FEE2006, Perugia Hans Krüger, University of Bonn 2 Counting and Integrating X-ray Detection (CIX) signal intensity Photon counter more information from the same x-ray dosage Integrator

FEE2006, Perugia Hans Krüger, University of Bonn 3 Pixel Concept Preamp Integrating Channel Conversion Layer Counting Channel Total deposited energy Number of absorbed photons Mean photon energy 

FEE2006, Perugia Hans Krüger, University of Bonn 4  Implementation

FEE2006, Perugia Hans Krüger, University of Bonn 5 Prototype chip CIX 0.1 chip features: AMS 0.35 µm CMOS technology area per electronics channel: 100 µm  547 µm linear arrangement of 17 cells (no bump bond pads) 2 test pixels with access to sub-circuits, e.g. preamplifier analog output in-pixel signal generation circuits (design for testability) low noise digital logic (low-swing differential current steering logic, DCL)

FEE2006, Perugia Hans Krüger, University of Bonn 6 Pixel Cell Block Diagram  Photon counting -preamp with continuous reset -replication of feedback current sourced to the integrator  Charge integration (I to F converter) -comparator output triggers charge pump (synchronous) -constant charge packet removed from integrator feedback capacitor C int -number of pump cycles and timestamps for first and last cycle stored  Signal simulation -switched capacitor and switched current charge injection circuits -internal/external dc current source

FEE2006, Perugia Hans Krüger, University of Bonn 7 Integrator: Charge Packet Counting f clk = 8 MHz pump cycles = 2 Time = 2560 I meas [pkts./clk] = 1/2560 = 0,0004 f clk = 8 MHz pump cycles = 2 Time = 853 I meas [pkts./clk] = 1/853 = 0,0012 Time  320µs Time  (1/3)*320µs Frame=320µs small current larger current U CINT t t

FEE2006, Perugia Hans Krüger, University of Bonn 8 Feedback Circuit feedback(fast) leakage current compensation (slow)  3 differential pairs: continuous reset of the CSA feedback capacitor signal replication to source the integrator leakage current compensation

FEE2006, Perugia Hans Krüger, University of Bonn 9 Charge injection circuits (chopper) chopper 1+2: switched capacitors (~10 fF), connected to preamplifier input current chopper: switched current source (800 nA max.), connected to preamplifier or integrator input minimal pulse duration ~30 ns leakage current simulation up to five load capacitors (~100 fF each) connected to preamplifier input

FEE2006, Perugia Hans Krüger, University of Bonn 10 Integrator and Charge Pumps switched capacitor charge pump: dQ = (VDDA - VIntRef) · 240 fF, typical charge packet 1.8 · 10 6 e - (i.e keV photons or 170 photons at 120 keV tube spectrum) 1.7µA maximal current throughput (at 6 MHz clock rate) switched current charge pump packet size controlled by IPump bias DAC and clock rate VIntTh controls charge pump trigger level

FEE2006, Perugia Hans Krüger, University of Bonn 11 Differential Current Mode Logic  Differential pair with constant bias current I bias -loads generate low voltage swings by I to U conversion  An ‘ideal’ load characteristic: -V hi level fixed at maximum possible input voltage (~VDD-V th –V Dsat ) -V low level fixed by the voltage swing required to ‘fully’ switch the current in the cell (~200 mV) -plateau at ½ I bias guarantees equal rise and fall times -and all this independent of the absolute value of I bias to match given loads and speed requirements Load I  U Load I  U out I bias in V hi V lo ½ I bias I load V load 'ideal' load characteristic I bias CML principle (inverter) P. Fischer, E. Kraft, “Low swing differential logic for mixed signal applications”, Nucl. Instr. Meth. A 518 (2004)

FEE2006, Perugia Hans Krüger, University of Bonn 12 Implementation of the load circuit  Approximation of the ideal load circuit -NMOS operated as a current source with adjustable voltage VSS -diode connected NMOS (or pn-diode) to ground  V hi increases only little with I bias  Differential swing can be adjusted through VSS bias VSSGND in V hi V lo ½ I bias I load V load Load I  U measured load characteristic

FEE2006, Perugia Hans Krüger, University of Bonn 13  Measurements

FEE2006, Perugia Hans Krüger, University of Bonn 14 Photon Counter Performance minimum operational threshold 500 e equivalent noise charge180 e + 79 e / 100 fF maximum count rate6 (12) MHz with static (dynamic) leakage current compensation double pulse resolution>100 ns

FEE2006, Perugia Hans Krüger, University of Bonn 15 Integrator Noise Performance perfect 12-bit ADC discretisation limit Poisson SNR limit

FEE2006, Perugia Hans Krüger, University of Bonn 16 Impact of the Feedback Circuit DIRECT injection via feedback  noise performance not optimal but Poisson statistics limits SNR for real X-ray photon detection (60 keV X-rays, CdTe sensor, 320 µs frame time): -100 pA  23 ph, sqrt(23) = 4,8 -1 nA  226 ph, sqrt(226) = nA  2260 ph, sqrt(2260) = 48 Poisson SNR limit

FEE2006, Perugia Hans Krüger, University of Bonn 17 Total Dynamic Range photon counter integrator overlap region 6 MHz max. pulse frequency 3 pA 66 pA 12 nA 200 nA a single pulse

FEE2006, Perugia Hans Krüger, University of Bonn 18 Reconstruction of the Mean Photon Energy total energy / photon count integrator lower limit photon counter overload original pulse size

FEE2006, Perugia Hans Krüger, University of Bonn 19 Summary  A readout scheme which is capable of simultaneous counting and integrating absorbed X-ray quanta has been proposed and implemented  The multi-stage feedback circuit of the pre-amplifier mirrors the signal current to the integrator and provides leakage current compensation  A prototype chip has been submitted and tested and showed the feasibility of the concept  The simultaneous operation is fully functional though still impaired by the excess noise of the (not optimized) feedback network  A new test chip has been submitted and is currently under study Acknowledgements: Edgar Kraft for the animated ppt – sildes References: E. Kraft et al., “Counting and Integrating Readout for Direct Conversion X-ray Imaging - Concept, Realization and First Prototype Measurement”, Proceedings of the IEEE 2005 NSS/MIC P. Fischer, E. Kraft, “Low swing differential logic for mixed signal applications”, Nucl. Instr. Meth. A 518 (2004)