This material exempt per Department of Commerce license exception TSU DSP Design Flows in FPGA

After completing this module, you will be able to: Objectives Describe the advantages and disadvantages of three different design flows Use HDL, CORE Generator, or System Generator for DSP depending on design requirements and familiarity with the tools Explain why there is a need for an integrated flow from system design to implementation Describe the System Generator and the tools it interfaces with Build a model, simulate it, generate VHDL, and go through the design flow Describe how Hardware in the Loop verification is beneficial in complex system design

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Upgrading to Sysgen 8.2 Summary Simulink Tips and Tricks

HDL Design Verification HDL Synthesis Implementation Download HDL Implement your design using VHDL or Verilog Functional Simulation Timing Simulation In-Circuit Verification Behavioral Simulation

Synthesis Design Verification Behavioral Simulation HDL Synthesis Implementation Download HDL Synthesize the design to create an FPGA netlist Functional Simulation Timing Simulation In-Circuit Verification

Implementation Design Verification Behavioral Simulation HDL Synthesis Implementation Download HDL Translate, place and route, and generate a bitstream to download in the FPGA Functional Simulation Timing Simulation In-Circuit Verification

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC HDL Co-Simulation Hardware Verification Resource Estimator Upgrading to Sysgen 8.2 Summary Simulink Tips and Tricks

CORE Generator Design Verification Behavioral Simulation Synthesis Implementation Download Functional Simulation Timing Simulation In-Circuit Verification HDL COREGen Instantiate optimized IP within the HDL code

Synthesize, Implement, Download Design Verification Behavioral Simulation Synthesis Implementation Download Functional Simulation Timing Simulation In-Circuit Verification COREGen Synthesize, Implement, and Download the bitstream, similar to the original design flow HDL

IP CENTER $P Additive White Gaussian Noise (AWGN) $P Reed Solomon $ 3GPP Turbo Code $P Viterbi Decoder P Convolution Encoder $P Interleaver/De-interleaver P LFSR P 1D DCT P 2D DCT P DA FIR P MAC P MAC-based FIR filter Fixed FFTs 16, 64, 256, 1024 points P FFT 16- to points P FFT - 32 Point P Sine Cosine Look-Up Tables $P Turbo Product Code (TPC) P Direct Digital Synthesizer P Cascaded Integrator Comb P Bit Correlator P Digital Down Converter P Asynchronous FIFO P Block Memory modules P Distributed Memory P Distributed Mem Enhance P Sync FIFO (SRL16) P Sync FIFO (Block RAM) P CAM (SRL16) P CAM (Block RAM) P Binary Decoder P Twos Complement P Shift Register RAM/FF P Gate modules P Multiplexer functions P Registers, FF & latch based P Adder/Subtractor P Accumulator P Comparator P Binary Counter P Multiplier Generator - Parallel Multiplier - Dyn Constant Coefficient Mult - Serial Sequential Multiplier - Multiplier Enhancements P Pipelined Divider P CORDIC Base Functions Memory Functions DSP Functions Math Functions Key: $ = License Fee, P = Parameterized, S = Project License Available, BOLD = Available in the Xilinx Blockset for the System Generator for DSP Xilinx IP Solutions

Xilinx CORE Generator List of available IP from or Fully Parameterizable

Relative Placement Other logic has no effect on the core Fixed Placement & Pre-defined Routing Guarantees Performance Guarantees I/O and Logic Predictability Fixed Placement I/Os Xilinx Smart-IP Technology 200 MHz Core Placement Number of Cores Device Size 200 MHz Pre-defined placement and routing enhances performance and predictability Performance is independent of:

Outputs.EDN (EDIF implementation netlist).XCO (core implementation data file / log file) Optional: –.ASY Foundation or Innoveda symbols –.VEO Verilog instantiation template –.V Verilog behavioral simulation model –.VHO VHDL instantiation template –.VHD VHDL behavioral simulation model

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Upgrading to Sysgen 8.2 Summary Simulink Tips and Tricks

The Challenges for a DSP Software Platform Industry Trends – Trend towards platform chips (FPGAs, DSP) resulting in greater complexity – Highly flexible systems required to meet changing standards – Multiple design methodologies - control plane/datapath – Challenges in modeling and implementing an entire platform – Hardware in the loop verification is useful in complex system design and System Generator supports it System Design Challenges – Leveraging legacy HDL code – Modeling & implementing control logic and datapath – No expert exists for all facets of system design

MATLAB MATLAB™, the most popular system design tool, is a programming language, interpreter, and modeling environment – Extensive libraries for math functions, signal processing, DSP, communications, and much more – Visualization: large array of functions to plot and visualize your data and system/design – Open architecture: software model based on base system and domain-specific plug-ins

MATLAB Frequency response of input sound file

Simulink Simulink™ - Visual data flow environment for modeling and simulation of dynamical systems – Fully integrated with the MATLAB engine – Graphical block editor – Event-driven simulator – Models parallelism – Extensive library of parameterizable functions Simulink Blockset - math, sinks, sources DSP Blockset - filters, transforms, etc. Communications Blockset - modulation, DPCM, etc.

MATLAB/Simulink Real time frequency response from a microphone: emphasizes the dynamic nature of Simulink

Traditional Simulink FPGA Flow GAP System Architect FPGA Designer Verify Equivalence HDL Synthesis Implementation Download Timing Simulation In-Circuit Verification Functional Simulation System Verification Simulink

System Generator for DSP Overview Industry’s system-level design environment (IDE) for FPGAs – Integrated design flow from Simulink to bit file – Leverages existing technologies Matlab/Simulink from The MathWorks HDL synthesis IP Core libraries FPGA implementation tools Simulink library of arithmetic, logic operators and DSP functions (Xilinx Blockset) – Bit and cycle true to FPGA implementation Arithmetic abstraction – Arbitrary precision fixed-point, including quantization and overflow – Simulation of double precision as well as fixed point

System Generator for DSP Overview VHDL code generation for Virtex-4™, Virtex-II Pro™, Virtex™-II, Virtex™-E, Virtex™, Spartan™-3E, Spartan™-3, Spartan™-IIE and Spartan™-II devices – Hardware expansion and mapping – Synthesizable VHDL with model hierarchy preserved – Mixed language support for Verilog – Automatic invocation of CORE Generator to utilize IP cores – ISE project generation to simplify the design flow – HDL testbench and test vector generation – Constraint file (.xcf), simulation ‘.do’ files generation – HDL Co-Simulation Verification acceleration using Hardware in the Loop

System Generator for DSP Platform Designs ISIM

The SysGen Design Flow 1. Develop Algorithm & System Model Download to FPGA DSP Development Flow 2. Automatic Code Generation Simulink MDL Bitstream 3. Xilinx Implementation Flow RTL VHDL & Cores HDL Test Bench ISIM Simulation

System Generator Based Design Flow HDL System Generator MATLAB/Simulink System Verification Synthesis Implementation Download Timing Simulation In-Circuit Verification Functional Simulation

System Generator Based Design Flow HDL System Generator MATLAB/Simulink System Verification Synthesis Implementation Download Timing Simulation In-Circuit Verification Functional Simulation HDL-CoSimulation Files Used Configuration file VHDL IP Constraints File * ModelSim helper block not needed when ISIM simulator is used

System Generator Based Design Flow HDL System Generator MATLAB/Simulink System Verification Files Used Configuration file VHDL IP Constraints File Synthesis Implementation Download Timing Simulation In-Circuit Verification Functional Simulation

Creating a System Generator Design Invoke Simulink library browser To open the Simulink library browser, click the Simulink library browser button or type “Simulink” in MATLAB console The library browser contains all the blocks available to designers Start a new design by clicking the new sheet button

Creating a System Generator Design Build the design by dragging and dropping blocks from the Xilinx blockset onto your new sheet. Design Entry is similar to a schematic editor Connect up blocks by pulling the arrows on the sides of each block

Finding Blocks Use the Find feature to search ALL Simulink libraries Xilinx blockset has nine major sections – Basic elements Counters, delays – Communication Error correction blocks – Control Logic MCode, Black Box – Data Types Convert, Slice – DSP FDATool, FFT, FIR – Index All Xilinx blocks – quick way to view all blocks – Math Multiply, accumulate, inverter – Memory Dual Port RAM, Single Port RAM – Tools ModelSim, Resource Estimator

Configure Your Blocks Double-click or go to Block Parameters to view a block’s configurable parameters – Arithmetic Type: Unsigned or twos complement – Implement with Xilinx Smart-IP Core (if possible)/ Generate Core – Latency: Specify the delay through the block – Overflow and Quantization: Users can saturate or wrap overflow. Truncate or Round Quantization – Override with Doubles: Simulation only – Precision: Full or the user can define the number of bits and where the decimal point is for the block – Sample Period: Can be inherent with a “-1” or must be an integer value Note: While all parameters can be simulated, not all are realizable

Values Can Be Equations You can also enter equations in the block parameters, which can aid calculation and your own understanding of the model parameters The equations are calculated at the beginning of a simulation Useful MATLAB operators – + add – - subtract – * multiply – / divide – ^ power –  pi ( …) – exp(x) exponential (ex)

Important Concept 1: The Numbers Game Simulink uses a “double” to represent numbers in a simulation. A double is a “64-bit twos complement floating point number” – Because the binary point can move, a double can represent any number between +/ x with a resolution of 1.08 x …a wide desirable range, but not efficient or realistic for FPGAs Xilinx Blockset uses n-bit fixed point number (twos complement optional) Design Hint: Always try to maximize the dynamic range of design by using only the required number of bits IntegerFraction Value = … Format = Fix_16_13 ( Sign: Fix = Signed Value UFix = Unsigned value) Format = Sign _ Width _ Decimal point from the LSB Thus, a conversion is required when communicating with Xilinx blocks with Simulink blocks (Xilinx blockset  MATLAB I/O  Gateway In/Out)

What About All Those Other Bits? The Gateway In and Out blocks support parameters to control the conversion from double precision to N - bit fixed point precision.. DOUBLE FIX_12_ QUANTIZATION OVERFLOW - Truncate - Round - Saturate - Wrap - Flag for Error

Other Type: Boolean The Xilinx Blockset also uses the type Boolean for control ports like CE and RESET The Boolean type is a variant on the 1-bit unsigned number in that it will always be defined (High or Low). A 1-bit unsigned number can become invalid; a Boolean type cannot

Knowledge Check Define the format of the following twos complement binary fraction and calculate the value it represents What format should be used to represent a signal that has: Fill in the table: Using the technique shown, convert the following fractional values… Format = Value = Format = a) Max value: … Min value: … Quantized to 12 bit data b) Max value: 0.8 Min value: 0.2 Quantized to 10 bit data c) Max value: 278 Min value: -138 Quantized to 11 bit data

Answers Define the format of the following twos complement binary fraction and calculate the value it represents What format should be used to represent a signal that has: Fill in the table: Using the technique below, convert the following fractional values Format = Value = -917 = Format = a) Max value: +1 Min value: -1 Quantized to 12-bit data b) Max value: 0.8 Min value: 0.2 Quantized to 10-bit data c) Max value: 278 Min value: -138 Quantized to 11-bit data

Creating a System Generator Design Simulink Sources Simulink Sinks Gateway blocks used to interface between Simulink and SysGen blocks SysGen Data Path and helper blocks

System Generator Design All SysGen design must contain a System Generator block Used to set global netlisting attributes Designs may have levels of hierarchy Double click to “push” into a subsystem Start simulation by pressing the play button

Important Concept 2: Sample Period Every SysGen signal must be “sampled”; transitions occur at equidistant discrete points in time called sample times Each block in a Simulink design has a “Sample Period” and it corresponds to how often that block’s function is calculated and the results outputted This sample period must be set explicitly for: Gateway in Blocks w/o inputs (note: constants are idiosyncratic) Sample period can be “derived” from input sample times for other blocks

Important Concept 2: Sample Period The units of the sample period can be thought of as arbitrary, BUT a lot of Simulink source blocks do have an essence of time – For example, a sample period of 1/44100 means the block’s function will be executed every 1/44100 of a sec Remember Nyquist Theorem (Fs  2f max ) when setting sample periods The sample period of a block DIRECTLY relates to how that block will be clocked in the actual hardware. More on this later

The Simulink System Period MUST be set in the System Generator token. For single rate systems it will be the same as the Sample Periods set in the design. More on Multi Rate designs later Setting the Global Sample Period Sample Period = 1

SysGen Token Master Controls Slave Controls “Simulink System Period” MUST be set correctly for simulation to work

Using the Scope Click Properties to change the number of axes displayed and the time range value (X-axis) Use the Data History tab to control how many values are stored and displayed on the scope – Also can direct output to workspace Click Autoscale to quickly let the tools configure the display to the correct axis values Right-click on the Y-axis to set its value

Design and Simulate in Simulink Push “play” to simulate the design. Go to “Simulation Parameters” under the “Simulation” menu to control the length of simulations

Generate the HDL Code Select the target device Select Synthesis Tool Set the FPGA clock period desired Select to generate the testbench Generate the VHDL Once complete, double-click the System Generator token

System Generator Output Files Design files –.VHD/.V : HDL design files – _cw.VHD/.V: Top-level HDL wrapper that contains clock circuit and SysGen Design –.EDN and.NGC: Core implementation file – _cw.XCF : Xilinx constraints file for timing and location constraints Project files – _cw.ISE : Project Navigator project file –.PRJ: Synthesis project files for XST and Synplify –.TCL : Scripts for Synplify and Leonardo project creation Simulation files –.DO : Simulation scripts for MTI –.DAT : Data files containing the test vectors from System Generator – _tb.VHD/.V : Simulation testbench

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Upgrading to Sysgen 8.2 Summary Simulink Tips and Tricks

Labs 1: Generating a MAC You will generate the MAC using the Xilinx System Generator for DSP Compare the implementation results Contrast the design methodologies

Lab 1 Goals: Gain familiarity with the SysGen v8.1 and its design flow, including ProjNav, synthesis tools (XST), ModelSim simulators, and the ISE implementation tools. Use Resource Estimator to estimate resources used by the design. Familiarize with hardware in the Loop flow Background: The multiply-accumulate (MAC) operation is fundamental in digital signal processing and numerous other applications For example, the output of a digital filter with impulse response h i and input sequence x i, is given by: + a b c y n =  x n-i h i i=0 N-1 c =  a i b i i

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Upgrading to Sysgen 8.2 Summary Simulink Tips and Tricks

Black Box Allows a way to import HDL models into System Generator Allows co-simulation of black box HDL with Simulink by using either ModelSim or ISE Simulator Integrates the imported HDL and implementation files (EDN, NGC) with the netlist generated from System Generator

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Upgrading to Sysgen 8.2 Summary Simulink Tips and Tricks

JTAG Hardware-in-the-loop development platforms: – Any board with a JTAG header Configure your JTAG-based board in 20 minutes Xilinx – XtremeDSP Development kit (Virtex-4, Virtex-II Pro) Also features high bandwidth interface via PCI – ML-401 and ML402 Boards (Virtex-4) – Multimedia Board (Virtex-II) Distributors: – Avnet, Insight, Nu Horizons Key board vendors: – Alphadata, Annapolis, Nallatech, Lyrtech High bandwidth interfaces Ethernet Hardware Co-simulation Choice of Target Hardware

Add Your Own Board in 20 Minutes Integrate your board into System Generator for hardware in the loop co-simulation Simple wizard collects information for your target platform

Hardware Co-simulation (1) Begin with a model that is ready to be compiled for hardware co-simulation. (2) Open the SysGen GUI and select a compilation target. (3) Press the Generate button in the SysGen GUI. (4) A post-generation function is invoked to produce an FPGA configuration file.

Hardware Co-simulation (5) The post-generation script creates a new library containing a parameterized run-time co-simulation block. (6) The co-simulation run- time block is copied into the original model. (7) The hardware output is bit and cycle accurate when compared to the original model.

– Provides remote access over a 10/100 Mbps network – Communication handled by EMAC OPB peripheral – Reconfiguration via Ethernet connection using MicroBlaze + SystemACE Ethernet Hardware Co-simulation Networked Ethernet hardware co- simulation FPGA Configuration FPGA Configuration

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Upgrading to Sysgen 8.2 Summary Simulink Tips and Tricks

WaveScope Debugging tool to visualize signals – Displays data in analog(a la Scope) and logic mode – Supports hex, decimal and binary radices – Allows cross-referencing signals in the model

Debugging the FPGA at System Speed (1) Insert Chipscope Pro blocks into your Simulink design Configure FPGA using JTAG interface Chipscope probes will be inserted into the FPGA Perform in-system debug at system speed

Debugging the FPGA at System Speed (2) Common Address Space New Shared Memory Interfaces – Allow multiple, independent resources (inside and outside Simulink) to share a common address space What types of resources? – FPGA hardware (co-simulation) – Simulink Blocks – MATLAB Console – Command Line Applications This makes for easy, in- system debugging

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC HDL Co-Simulation Hardware Verification In System Debug Resource Estimator Upgrading to Sysgen 8.2 Summary Simulink Tips and Tricks

Resource Estimator The block provides fast estimates of FPGA resources required to implement the subsystem Most of the blocks in the System Generator Blockset carries the resources information – LUTs – FFs – BRAM – Embedded multipliers – 3-state buffers – I/Os

Resource Estimator Three types of estimation – Estimate Area This option computes resources for the current level and all sub-levels – Quick Sum Uses the resources stored in block directly and sum them up (no sub-levels functions are invoked) – Post-Map Area Opens up a file browser and let user select map report file. The design should have been generated and gone through synthesis, translate, and mapping phases.

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC Hardware Verification In System Debug Resource Estimator Upgrading to Sysgen 8.2 Summary Simulink Tips and Tricks

Migrating Existing Models to 8.1 xlUpdateModel – Required to use an existing Sysgen model in 8.1 Self modifying diagrams require manual intervention

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC Hardware Verification In System Debug Resource Estimator Upgrading to Sysgen 8.1 Summary Simulink Tips and Tricks

Summary Full VHDL/Verilog (RTL code) – Advantages: Portability Complete control of the design implementation and tradeoffs Easier to debug and understand a code that you own – Disadvantages: Can be time-consuming Don’t always have control over the Synthesis tool Need to be familiar with the algorithm and how to write it Must be conversant with the synthesis tools to obtain optimized design

Summary Full VHDL/Verilog (Instantiating Primitives) – Advantages: Full access to all architecture features Carry on further with optimization Best optimization – Disadvantages: Not as portable as RTL VHDL/Verilog Must be an FPGA expert and know the architecture Time-consuming

Summary CORE Generator – Advantages Can quickly access and generate existing functions No need to reinvent the wheel and re-design a block if it meets specifications IP is optimized for the specified architecture – Disadvantages IP doesn’t always do exactly what you are looking for Need to understand signals and parameters and match them to your specification Dealing with black box and have little information on how the function is implemented

Summary System Generator for DSP – Advantages Huge productivity gains through high-level modeling Ability to simulate the complete designs at a system level Very attractive for FPGA novices Excellent capabilities for designing complex testbenches HDL Testbench, test vector and golden data written automatically Hardware in the loop simulation improves productivity and provides quick verification of the system functioning correctly or not – Disadvantages Minor cost of abstraction: doesn’t always give the best result from an area usage point of view Customer may not be familiar with Simulink Not well suited to multiple clock designs No bi-directional bus supported

Outline Using HDL Using the Xilinx CORE Generator Using the Xilinx System Generator for DSP Lab 1: Creating a 12x8 MAC Hardware Verification In System Debug Resource Estimator Summary Simulink Tips and Tricks

Throughout this course, we will disperse various tips and tricks that we find useful when using Simulink to create System Generator designs

Complete Systems Throughout this course, we will build and study small sections of complete systems To get a flavor of the capability of System Generator, check out the demos Type “demos” from the MATLAB command line to view them

Combining Signals To be viewed on a scope, multiple signals must first be combined Use the MUX block (Simulink library  Signals & Systems) to combine signals, thus making a vector out of them Check Format  Signal Dimensions and Format  Wide NonScalar Lines to view how many signals are combined Similarly, the DEMUX can be used to separate signals Type ‘vector’ to view the example

Creating Subsystems All large designs will utilize hierarchy Select the blocks to go into the subsystem. Click and drag to highlight a design region Select “Create Subsystem” in the Edit Menu – Ctrl+G has the same effect Use the modelbrowser under the “View” menu to navigate the hierarchy Hierarchy in the VHDL code generated is determined by subsystems

Documenting a Design Double-click the background to create a textbox Type in the text Right-click the text to change format Left-click to move the textbox around A masked subsystem can be given “Help” documentation. More on this later

Inports and Outports Allow the transfer of signal values between a subsystem and a parent Inport and Outport block names are reflected on the subsystem Can be found in Simulink  Sinks (for the Outport) and Simulink  Sources (for the Inport)

Inputting Data from the Workspace “From Workspace” block can be used to input MATLAB data to a Simulink model Format: – t = 0:time_step:final_time; – x = func(t); – make these into a matrix for Simulink Example: – In the MATLAB console, type: t = 0:0.01:1; x = sin(2*pi*t); simin = [t', x']; Type ‘FromWorkspace’ to view the example

Outputting Data to the Workspace “To Workspace” block can be used to output a signal to the MATLAB workspace The output is written to the workspace when the simulation has finished or is paused Data can be saved as a structure (including time) or as an array Type ‘ToWorkspace’ to view the example