Chapter Twelve Memory Organization

Memory Hierarchy Magnetic tapes Main memory I/O processor Magnetic discs Auxiliary memory Cache CPU

Auxiliary vs. Main Memory Provides backup storage Low-cost Large capacity Holds data file, system programs, etc not currently needed No direct access by CPU Holds programs and data currently needed Smaller capacity Direct access by CPU Higher cost Faster access, but still not fast enough…

Cache Memory Very-high speed memory Smaller capacity, higher cost Access time is close to processor logic clock cycle time Stores program segments currently being executed and data frequently accessed Increases performance of computer

Memory Hierarchy • Get the performance of fast expensive memory for the price of slow cheap memory! • GP Registers (2-5 ns) • Cache • Level 1 Cache (2-10 ns) • Level 2 Cache (5-20 ns) • Main Memory (40–80 ns) • Disk (10 ms seek, 5-100 Mb/s throughput)

Foundations • Convention: Registers are lowest, Disk is highest • Inclusion: Data found at one level of the hierarchy is also found at all higher levels • A miss at level i implies data is not at any lower level • Coherence: Copies of data at multiple levels of the hierarchy must (eventually) be consistent • Write through • Write back • Locality • Temporal: Recently accessed items are likely to be accessed • Spatial: Items that are close in address are likely to be accessed

Basic Operation of Cache When CPU needs to access memory, first checks cache If found, then it is a hit -- data is read If not found, then it is a miss -- access main memory and transfer block to cache

Metrics Hit ratio: hi is the probability that a datum is present at at level i • Access frequency: fi = (1-h1)(1-h2) …. (1-hi-1)hi Effective access time: Teff = sum fi*ti

Goals Performance = level 1 Cost per bit = level n Overall performance  effective hierarchical access time per memory reference is small Foundation is based on locality

Mapping Procedures Associative mapping – fastest and most flexible Direct mapping – most rigid Set-associative mapping – compromise between the two

Replacement Policies Choose the victim: • Least Recently Used (LRU) • Least Frequently Used (LFU) • First In First Out (FIFO) • Random • Optimal

Analysis of Write-Back Simple Write-Back – all replaced pages are written back to disk Average reference time is Tm + 2(1-h)Tp Where Tm is the memory access time for one word Tp is the page transfer time 2  one for loading and a for writing back

Flagged Write Back Use dirty bit, set when a page is modified Write back only if it is dirty Average reference time = Tm + (1-h) (Tp +Wp * Tp) Where Wp is the probability that a page is modified

Write-through Update main memory and disk same time Main memory always has the same data as disk Page is loaded on a write-miss and read miss Ave. time = Tm + (1-h)Tp + Wt (Td-Tm) Where Wt is the fraction of writes and Td is the disk access time