Mark Raymond /12/051 Trip-t & TFB Trip-t schematics signals and registers operation SiPM connection TFB block diagram functionality (slow control and FE-FPGA)

Mark Raymond /12/052 Trip-t schematics - overview from “Bench test of TRIP-t” Leo Bellantoni & Paul Rubinov

Mark Raymond /12/053 Trip-t schematics – front end only 2 gain settings to preamp (1 & 4) preamp output goes straight to discriminator (global threshold) could be awkward if widely varying SiPM gains other gain settings only affect signals to pipeline from “Bench test of TRIP-t” Leo Bellantoni & Paul Rubinov

Mark Raymond /12/ pin 14 x 14 mm QFP analog I/Ps digital disc O/Ps digital control I/Ps analog test I/P analog bias (dec.) analog O/P test I/P only +2.5V gnd not used Trip-t pinout

Mark Raymond /12/055 Trip-t control signals PrgReset resets programming interface PrgCtrl defines whether programming the chip or running the output MUX PrgIn serial programming info or MUX reset (depending on PrgCtrl) PrgOut serial output to read back programmed register values PrgClk shift in serial programming data or MUX clock (depending on PrgCtrl) PR1Triggers pipeline readout PlnClkPipeline clock PlnResetResets the pipeline MoveDataClears triggered pipeline column (allows timeslice to be overwritten) SkipBTriggers the pipeline (stops timeslice of interest being overwritten) PR2Pipeline pedestal acquisition (not used – left over from SVX) PreResetSwitches preamplifiers between integrate/reset Pre2aReset complement of PreReset Pre2bReset complement of PreReset DigenLenables one bank of 16 discriminator outputs off-chip DigenUenables the other bank DigResetBresets the discriminators dual fast/slow functionality here

Mark Raymond /12/056 Trip-t registers programming chip ID: register address: 5 bits operation: 3 bits (read/write/set/reset/default) 1 bit space value: 8/10/34 bits

Mark Raymond /12/057 Trip-t operation during spill discriminator fires PlnClk PreReset beam bunches end of spill SkipB programmed bunch latency PlnReset need to continue clocking pipeline beyond end of spill until latency has elapsed (might be an event in last bunch) event PlnClk transfers preamp output to pipeline at end of integration period Pipeline internal write (and trigger) pointer then advances to next timeslice Pipeline trigger pointer points to timeslice that was written the programmed bunch latency before When SkipB applied the timeslice that the trigger pointer is pointing to is marked to not be overwritten (the write pointer will skip over it the next time it comes round) and its address is stored in a fifo (only 4 deep)  only 4 timeslices can be triggered in a particular spill (you can return triggered timeslices to normal operation by applying MoveData signal after the timeslice data have been MUXed out, so could continuosly trigger and read out chip, but taking care not to have more than 4 triggered timeslices in the pipeline at any one time)

Mark Raymond /12/058 At end of spill run the MUX MUX reset, and then MUX clock simultaneously control ADC clock and ADC output MUX (2 ADC channels share 10 bit O/P parallel data bus) specified (D0) ADC can run at 20 MHz =>1 timeslice can be read out in 32 x 50 ns = 1.6 usec (+ a bit for MUX reset) don’t necessarily have to wait till end of spill, could run MUX and Preamp/Pipeline simultaneously just have to take care not to overtrigger (fifo depth) but may be preferable to have separate acquisition/readout phases

Mark Raymond /12/059 SiPM connection connection method Vbias 1 M  50  thin coax SiPM LED trip-t 3p3 330p SiPM -> Tript cable: have used coax mostly up to now SiPM connected between core and coax sheath (core carries bias voltage) Coax provides signal shielding, twisted pair doesn’t – could we use shielded twisted pair? 50  provides some kind of termination for the cable (-> 100  for twisted pair) charge split between two tript channels using different capacitor values to get high/low gain feed in small current here to tune Vbias for individual SiPM’s or twisted pair

Mark Raymond /12/0510 SiPM connection (analogue issues) Tript with high preamp gain setting (1pF feedback) high gain saturates at ~ 1pC, low gain at ~ 15 pC (for charge splitting cap. values on p. 10) can we use SiPM HV trim to tune individual SiPM gains to match these ranges? how well will final SiPM gains have to match? how well do SiPM gains really have to match?

Mark Raymond /12/0511 TFB TripT SiPM x16 FE-FPGA  controller ADC HVTrimDAC 8 8 TripT SiPM x16 HVTrimDAC 8 8 TripT SiPM x16 HVTrimDAC 8 8 TripT SiPM x16 HVTrimDAC 8 8 local power conditioning slow serial I/F fast serial data timing temperature monitoring low voltage monitoring high voltage monitoring calibration

Mark Raymond /12/0512 micro-controller functionality (slow control) looks after programming of front end chips (internal LUT contains operational values) at power on, and on external request needs to communicate with FE-FPGA - Tript programming inputs share pins with MUX control signals monitor local (TFB) low and high (for TFB, not for every SiPM) voltage levels using internal, multi-input ADC monitor local environment (obviously temperature but anything else…?) may need external sensors Trip-t & electronic chain calibration (independent of SiPM) using Tript input channel mask register and external DAC can inject programmable amplitude test pulses into individual channels need to synchronize with FE-FPGA slow interface to outside – could be custom, could be commercial (e.g. I 2 C?) generate alarm (e.g. over-temperature) will we want to be able to re-program micro-controller in TFB production version? clearly this functionality could be implemented in FE-FPGA would then need extra service chips (at least a multi-channel ADC) keeping data and control paths separate usually considered good thing

Mark Raymond /12/0513 FE-FPGA functionality (fast control) Synchronization to accelerator (spill structure and bunch clock) (how?) Tript operation during spill provide clocks (preamp integrate/reset and pipeline) timestamp discriminator outputs and return trigger (SkipB) to mark pipeline timeslices to be subsequently read out (max 4 per spill (depth of Tript FIFO)) At end of spill (after pipeline latency elapsed) Run Tript MUX and ADC to read out triggered timeslices acquire digitized data time required = 32 x no. of triggers x mux clock period (50ns say) = 1.6 usec x no. of triggers format data and transmit (later slide) During spill gap (~ 3 secs.) look for cosmics free run Tript – continuous pipeline cycling trigger in same way as during spill, but also pass triggers off board (do we need to construct local track trigger?) (do we need to wait for return of trigger accept signal from outside?) Run MUX and ADC for every trigger, format data and transmit should be able to be live for high percentage of time (trigger rate << 1 per 1.6 usec)

Mark Raymond /12/0514 What to do with spill (and cosmic) data in FE-FPGA? – some options here 1) minimal processing attach timestamp, bunch no., individual TFB ID, raw data and transmit everything (will want option to operate in this mode for debugging) 2) more processing pedestal subtract, suppress channels with no signal (vast majority), attach timestamp, bunch no, individual SiPM no., individual TFB ID, signal amplitude, and transmit Where / how / how often to construct s.p.e. spectra for SiPM gain calibration? does this need to be done in FE-FPGA? - complicated thing to have to do comes with raw data anyway - s.p.e. noise hits in channels without signal could insist on raw data transmission outside spill time (make this an off- detector task?) could locally generate dummy triggers at some rate but may conflict with cosmic event acceptance