Architectural Characterization of an IBM RS6000 S80 Server Running TPC-W Workloads Lei Yang & Shiliang Hu Computer Sciences Department, University of Wisconsin-Madison

Outline TPC-W Benchmarks in JavaTPC-W Benchmarks in Java IBM RS6000 S80 Enterprise ServerIBM RS6000 S80 Enterprise Server Hardware Counters in S80Hardware Counters in S80 Experiment ResultsExperiment Results Problems and Future workProblems and Future work ConclusionsConclusions

TPC-W benchmark TPC-W is the TPC’s new benchmark for Transactional Web Environments (E-Commerce) Modeling an online book store similar to –Browsing 95% browsing, 5% transactions –Shopping 80% browsing, 20% transactions –Ordering 50% browsing, 50% transactions Transactional Web Environment: –Web serving of static and dynamic content –Online Transaction processing (OLTP) –Some decision support (DSS)

IBM RS6000 S80 Enterprise Server 6 RS64-III Pulsar processors (451MHz)6 RS64-III Pulsar processors (451MHz) –4-issue in-order Super Scalar microprocessor with on chip 128KB L1 I-Cache, 128KB L1 D-Cache and 8MB L2 Cache. –No Branch Prediction, Aggressive early branch resolution –2 coarse grain Multithreading. SMP system. Snooping bus inter-processor connection.SMP system. Snooping bus inter-processor connection. 8GB main memory and large disk volumes. And high bandwidth IO systems.8GB main memory and large disk volumes. And high bandwidth IO systems.

System Configuration: RS64-III processor 32bits Control word RS64-III processor 32bits Control word AIX kernel Kernel Extension Performance Monitor Snooping bus Java Virtual Machine Emulated Browser Java Virtual Machine DB2 DBMS Processes JDBChttp SUN Java Web Server2.0 Java Servlet

Hardware Counters in S80 3 major components3 major components - 8 Built-in hardware counters in each RS64-III processor. - Kernel extension to AIX Performance Monitor API in the next release of AIX. 3 level counting with their own counting contexts:3 level counting with their own counting contexts: - System level counting, whole system level context - Process / Process group, process level context - Individual thread, thread level context. Some Problems with current version. - Cannot counter for individual processor. - Some Listed events are not available.

Hardware Counters in S80 Processor eventsProcessor events - execution cycles and the number of instructions executed. Instruction mix eventsInstruction mix events - Pipeline M, S, B and S instructions executed. Branch eventsBranch events - Conditional branch T/NT events, unconditional branches, zero cycle branches. Address Translation eventsAddress Translation events - TLB/SLB and ERAT/IERAT miss and duration events. Cache eventsCache events - Cache misses and latencies for each of the L1 I-Cache L1 D-Cache L2 Cache Bus and multi-processor bus snooping eventsBus and multi-processor bus snooping events - bus utilization. multi-processor bus snooping events

Results: IPC for RBE, JavaWebServer and DB2

Results: Instruction Dispatch

Results: Instruction Mix

Results: Branch Behavior

Results: Cache Behavior

Problems & Future Works Problems: - Large Dataset - Network and Server end software are the bottleneck? - Hardware counters vs. Simulations. Future works: - Measurement of other transactional processing and web serving benchmarks for comparison. - More architectural characterizations such as multithreaded processors, multiprocessor snooping and scaling.

Conclusions Server end Software is critical for high-end servers - Network and Server end software are the bottleneck - This is true for Preliminary performance characterization shows: - CPU utilization is highly dependent upon the application workloads. - High dispatching mechanism on RS64III appears less efficiently used. - Branch behavior is web interactions dependent. - L2 cache miss rate is unreasonably low and

Acknowledgement