Copyright Agrawal, 2009ELEC / Spr 09, Lecture 61 ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Power Analysis and Process Variation Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Process Variation in Nanoscale Devices Nanoscale device have dimensions smaller than 100 nm, typically, 65nm, 45nm, 32nm, 22nm, etc. Nanoscale device have dimensions smaller than 100 nm, typically, 65nm, 45nm, 32nm, 22nm, etc. As geometries become closer to molecular dimensions, percentage random variation in parameters become large. As geometries become closer to molecular dimensions, percentage random variation in parameters become large. Affected physical parameters: transistor width (W) and length (L), interconnect width and spacing, doping level. Affected physical parameters: transistor width (W) and length (L), interconnect width and spacing, doping level. Affected electrical characteristics: on and off resistances of transistors, threshold voltage and leakage current, capacitances. Affected electrical characteristics: on and off resistances of transistors, threshold voltage and leakage current, capacitances. Major influence on gate delays, ±20%, or more. Major influence on gate delays, ±20%, or more. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 62

Dynamic Power and Process Variation Dynamic power increases with glitch transitions, which are functions of gate delays. Dynamic power increases with glitch transitions, which are functions of gate delays. Process variation can influence delays in a circuit, especially in nanoscale technologies. Process variation can influence delays in a circuit, especially in nanoscale technologies. Monte Carlo simulation used to address the variation is time consuming and expensive. Monte Carlo simulation used to address the variation is time consuming and expensive. Bounded delay models are usually considered to address process variations in logic level simulation and timing analysis. Bounded delay models are usually considered to address process variations in logic level simulation and timing analysis. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 63

References Simulation: Simulation: S. Chakraborty and D. L. Dill, “More Accurate Polynomial-Time Min- Max Timing Simulation,” Proc. 3 rd International Symp. Advanced Research in Asynchronous Cir. and Syst., Apr. 1997, pp S. Chakraborty and D. L. Dill, “More Accurate Polynomial-Time Min- Max Timing Simulation,” Proc. 3 rd International Symp. Advanced Research in Asynchronous Cir. and Syst., Apr. 1997, pp J. W. Bierbauer, J. A. Eiseman, F. A. Fazal, and J. J. Kulikowski, “System Simulation With MIDAS,” AT&T Tech. J., vol. 70, no. 1, pp. 36–51, Jan J. W. Bierbauer, J. A. Eiseman, F. A. Fazal, and J. J. Kulikowski, “System Simulation With MIDAS,” AT&T Tech. J., vol. 70, no. 1, pp. 36–51, Jan S. Bose, H. Grimes, and V. D. Agrawal, “Delay Fault Simulation With Bounded Gate Delay Model,” Proc. International Test Conf., 2007, pp. 23–28. S. Bose, H. Grimes, and V. D. Agrawal, “Delay Fault Simulation With Bounded Gate Delay Model,” Proc. International Test Conf., 2007, pp. 23–28. Timing anlysis: Timing anlysis: S. Chakraborty, D. L. Dill, and K. Y. Yun, “Min-Max Timing Analysis and an Application to Asynchronous Circuits,” Proc. IEEE, vol. 87, no. 2, pp. 332–346, Feb S. Chakraborty, D. L. Dill, and K. Y. Yun, “Min-Max Timing Analysis and an Application to Asynchronous Circuits,” Proc. IEEE, vol. 87, no. 2, pp. 332–346, Feb Delay fault testing: Delay fault testing: H. Grimes, Reconvergent Fanout Analysis of Bounded Gate Delay Faults, Master’s thesis, Auburn University, Dept. of ECE, Aug H. Grimes, Reconvergent Fanout Analysis of Bounded Gate Delay Faults, Master’s thesis, Auburn University, Dept. of ECE, Aug Copyright Agrawal, 2009ELEC / Spr 09, Lecture 64

Problem Statement Given a set of vectors (random or functional), determine the range of dynamic power consumption for specified bounds on delay variation. Given a set of vectors (random or functional), determine the range of dynamic power consumption for specified bounds on delay variation. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 65

Power Analysis Methods Monte Carlo simulation: Monte Carlo simulation: R. Burch, F. Najm, P. Yang, and T. Trick, “McPOWER: A Monte Carlo Approach to Power Estimation,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 90– 97, Nov R. Burch, F. Najm, P. Yang, and T. Trick, “McPOWER: A Monte Carlo Approach to Power Estimation,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 90– 97, Nov Bounded-delay analysis: Bounded-delay analysis: J. D. Alexander, Simulation Based Power Estimation for Digital CMOS Technologies, Master’s thesis, Auburn University, Dept. of ECE, Dec J. D. Alexander, Simulation Based Power Estimation for Digital CMOS Technologies, Master’s thesis, Auburn University, Dept. of ECE, Dec Copyright Agrawal, 2009ELEC / Spr 09, Lecture 66

C880: Monte Carlo Simulation Copyright Agrawal, 2009ELEC / Spr 09, Lecture 67 Min Power (mW) Max Power (mW) CPU Time (secs) Random Vectors, 1000 Sample Circuits ± 20% random delay variation

Bounded Delay Model Model delay uncertainties by assigning each gate a lower and an upper bound on delay, also known as min-max delay. Model delay uncertainties by assigning each gate a lower and an upper bound on delay, also known as min-max delay. The bounds can be obtained by adding specified process-related variation to the nominal gate delay for the technology. The bounds can be obtained by adding specified process-related variation to the nominal gate delay for the technology. In this model, intervals of signal uncertainties are defined at the output of each gate. In this model, intervals of signal uncertainties are defined at the output of each gate. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 68

Ambiguity Delay Intervals Copyright Agrawal, 2009ELEC / Spr 09, Lecture 69 EA is the earliest arrival time LS is the latest stabilization time IV is the initial signal value FV is the final signal value IVFV LSEA IVFV EALS mindel, maxdel EAdvLSdv EAsv=-∞ LSsv=∞ EAsvLSsv EAdv=-∞LSdv=∞ ?

Sensitizing and Driving Values Relative to Gate a Signal Feeds Into Copyright Agrawal, 2009ELEC / Spr 09, Lecture 610 mindel, maxdel EAdvLSdv EAsv=-∞ LSsv=∞ EAsvLSsv EAdv=-∞ LSdv=∞ ? Earliest possible termination of sensitization value Definite termination of sensitization value Sensitizing value (sv) Driving value (dv)

Propagating Ambiguity Intervals through Gates Copyright Agrawal, 2009ELEC / Spr 09, Lecture 611 The ambiguity interval (EA,LS) for a gate output is determined from the ambiguity intervals of input signals, their pre- transition and post-transition steady-state values, and the min-max gate delays. (mindel, maxdel)

Summarize Input Signals To evaluate the output of a gate, we analyze inputs i: To evaluate the output of a gate, we analyze inputs i: Copyright Agrawal, 2009ELEC / Spr 09, Lecture 612

Use Inertial Delay of Gate Ambiguity interval at gate output: Ambiguity interval at gate output: where the inertial delay of the gate is bounded as (mindel, maxdel). where the inertial delay of the gate is bounded as (mindel, maxdel). Copyright Agrawal, 2009ELEC / Spr 09, Lecture 613

Finding Number of Transitions Copyright Agrawal, 2009ELEC / Spr 09, Lecture , (mindel, maxdel) EA LS 3 14 EA LS [0,4] [0,2] 6 17 EA LS [mintran,maxtran] where mintran is the minimum number of transitions and maxtran the maximum number of transitions.

Estimating maxtran Nd: First upper bound is the largest number of transitions that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV, FV) output values. Nd: First upper bound is the largest number of transitions that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV, FV) output values. N: Second upper bound is the sum of the input transitions as the output cannot exceed that. Further modify it as N: Second upper bound is the sum of the input transitions as the output cannot exceed that. Further modify it as N = N – k N = N – k where k = 0, 1, or 2 for a 2-input gate and is determined by the ambiguity regions and (IV, FV) values of inputs. The maximum number of transitions is lower of the two upper bounds: The maximum number of transitions is lower of the two upper bounds: maxtran = min (Nd, N) maxtran = min (Nd, N) Copyright Agrawal, 2009ELEC / Spr 09, Lecture 615

Effect of Gate Inertial Delay Copyright Agrawal, 2009ELEC / Spr 09, Lecture 616 D W D << W D < W D ≈ W D > W

First Upper Bound, Nd Nd = 1 + (LS – EA)/mindel Nd = 1 + (LS – EA)/mindel └ ┘ └ ┘ Copyright Agrawal, 2009ELEC / Spr 09, Lecture 617 mindel, maxdel EA LS mindel

Examples of maxtran (k = 0) Copyright Agrawal, 2009ELEC / Spr 09, Lecture 618 Nd = ∞ N = 8 maxtran=min (Nd, N) = 8 Nd = 6 N = 8 maxtran=min (Nd, N) = 6

Example: maxtran With Non-Zero k Copyright Agrawal, 2009ELEC / Spr 09, Lecture 619 EAsv = - ∞ EAdv LSdv = ∞ LSsv EAsv = - ∞ LSdv = ∞ EAdvLSsv EALS [n1 = 6] [n2 = 4] [n1 + n2 – k = 8 ], where k = 2 [ 6 ] [ 4 ] [ – 2 = 8 ]

Estimating mintran Ns: First lower bound is based on steady state values, IV  FV, Ns: First lower bound is based on steady state values, IV  FV, If 0  0 or 1  1, then Ns = 0 If 0  0 or 1  1, then Ns = 0 If 0  1 or 1  0, then Ns = 1 If 0  1 or 1  0, then Ns = 1 In case of split ambiguity intervals, separate Ns is obtained for each interval and then all are added up In case of split ambiguity intervals, separate Ns is obtained for each interval and then all are added up Ndet: Second lower bound is the minimum number of transitions permitted by the maximum inertial delay of the gate (maxdel). Ndet: Second lower bound is the minimum number of transitions permitted by the maximum inertial delay of the gate (maxdel). The minimum number of transitions is the higher of the two lower bounds: The minimum number of transitions is the higher of the two lower bounds: mintran = max (Ns, Ndet) mintran = max (Ns, Ndet) Copyright Agrawal, 2009ELEC / Spr 09, Lecture 620

Example: mintran There will always be a hazard in the output as long as There will always be a hazard in the output as long as (EAsv – LSdv) ≥ maxdel Thus in this case the mintran is not 0 as per the steady state condition, but is 2. Thus in this case the mintran is not 0 as per the steady state condition, but is 2. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 621 d EAsv = - ∞ EAdv LSsv = ∞ LSdv EAdv = - ∞ LSdv = ∞ EAsvLSsv EALS (mindel, maxdel)

Multiple Ambiguity Intervals Multiple ambiguity intervals are waveform containing intermittent regions of deterministic signal states. Multiple ambiguity intervals are waveform containing intermittent regions of deterministic signal states. We arrange the (EA, LS) values at the gate inputs in order of their temporal occurrences. We arrange the (EA, LS) values at the gate inputs in order of their temporal occurrences. If an (LS) value occurs before an (EA) value, then multiple ambiguity are separated by a deterministic value. If an (LS) value occurs before an (EA) value, then multiple ambiguity are separated by a deterministic value. We propagate the split ambiguity intervals to the output on the condition that the deterministic interval is longer than the gate inertial delay. We propagate the split ambiguity intervals to the output on the condition that the deterministic interval is longer than the gate inertial delay. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 622

Example Copyright Agrawal, 2009ELEC / Spr 09, Lecture 623 d1,d2 EA1+ d1LS3 + d2 d1,d2 EA1LS1 EA2LS2 EA3LS3 EA1LS1 EA2LS2 EA3LS3 EA1+ d1EA3 + d1 LS3 + d2LS2 + d2 Without ordering input ambiguity intervals. Ordering of input ambiguity intervals.

Simulation Methodology maxdel, mindel = nominal delay ± Δ% maxdel, mindel = nominal delay ± Δ% Three linear-time passes for each input vector: Three linear-time passes for each input vector:  First pass: zero delay simulation to determine initial and final values, IV and FV, for all signals.  Second pass: determines earliest arrival (EA) and latest stabilization (LS) from IV, FV values and bounded gate delays.  Third pass: determines upper and lower bounds, maxtran and mintran, for all gates from the above information. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 624

Effect of Gate Delay Distribution Experiment conducted to see if the distribution of gate delays has an effect on power distribution. Experiment conducted to see if the distribution of gate delays has an effect on power distribution. For uniform distribution: Gate delays were randomly sampled from uniform distribution [a, b], where a = nominal delay – Δ % and b = nominal delay + Δ % This distribution has a variance σ 2 = (b – a) 2 /12 = Δ 2 (nom. delay) 2 /30,000. For uniform distribution: Gate delays were randomly sampled from uniform distribution [a, b], where a = nominal delay – Δ % and b = nominal delay + Δ % This distribution has a variance σ 2 = (b – a) 2 /12 = Δ 2 (nom. delay) 2 /30,000. For normal distribution: Gate delays were randomly sampled from a Gaussian density with mean = nom. delay, and variance σ 2 as above. For normal distribution: Gate delays were randomly sampled from a Gaussian density with mean = nom. delay, and variance σ 2 as above. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 625

Monte Carlo Experiment Copyright Agrawal, 2009ELEC / Spr 09, Lecture 626 A standard gate node delay of 100 ps was taken. A wire load delay model was followed with each nominal gate delay being a function of its fan-out. A standard gate node delay of 100 ps was taken. A wire load delay model was followed with each nominal gate delay being a function of its fan-out. The power distribution is for 1000 random vectors with a vector period of ps. The power distribution is for 1000 random vectors with a vector period of ps. For each vector pair 1000 sample circuits were simulated. For each vector pair 1000 sample circuits were simulated.

Copyright Agrawal, 2009ELEC / Spr 09, Lecture 627 Normal Distribution Uniform Distribution

Experimental Result (Maximum Power) Monte Carlo Simulation vs. Min-Max analysis for circuit C sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors). Monte Carlo Simulation vs. Min-Max analysis for circuit C sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors). Copyright Agrawal, 2009ELEC / Spr 09, Lecture 628 R 2 is coefficient of determination, equals 1.0 for ideal fit.

Result…(Minimum Power) Copyright Agrawal, 2009ELEC / Spr 09, Lecture 629 R 2 is coefficient of determination, equals 1.0 for ideal fit.

Results…(Average Power) R 2 is coefficient of determination, equals 1.0 for ideal fit. Copyright Agrawal, ELEC / Spr 09, Lecture 6

C880: Monte Carlo vs. Bounded Delay Analysis Copyright Agrawal, 2009ELEC / Spr 09, Lecture 631 Monte Carlo SimulationBounded Delay Analysis Min Power (mW) Max Power (mW) CPU Time (secs) Min Power (mW) Max Power (mW) CPU Time (secs) Random Vectors, 1000 Sample Circuits

Power Estimation Result Circuits implemented using TSMC V CMOS library, with standard size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained by assuming ± 20 % variation. The simulation was run on a UNIX operating system using a Intel Duo Core processor with 2 GB RAM. Circuits implemented using TSMC V CMOS library, with standard size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained by assuming ± 20 % variation. The simulation was run on a UNIX operating system using a Intel Duo Core processor with 2 GB RAM. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 632

Conclusion Bounded delay model allows power estimation method with consideration of uncertainties in delays. Bounded delay model allows power estimation method with consideration of uncertainties in delays. Analysis has a linear time complexity in number of gates and is an efficient alternative to the Monte Carlo analysis. Analysis has a linear time complexity in number of gates and is an efficient alternative to the Monte Carlo analysis. Copyright Agrawal, 2009ELEC / Spr 09, Lecture 633

Future Refinements Consider process dependent variations in leakage and in node capacitances. Consider process dependent variations in leakage and in node capacitances. Use statistical methods to determine distributions of average and peak power consuming circuits. See following references: Use statistical methods to determine distributions of average and peak power consuming circuits. See following references: V. Bartkute and L. Sakalauskas, “Three Parameter Estimation of the Weibull Distribution by Order Statistics,” in C. H. Skiadas, editor, Recent Advances in Stochastic Modeling and Data Analysis, pp. 91–100, World Scientific, V. Bartkute and L. Sakalauskas, “Three Parameter Estimation of the Weibull Distribution by Order Statistics,” in C. H. Skiadas, editor, Recent Advances in Stochastic Modeling and Data Analysis, pp. 91–100, World Scientific, Q. Qiu, Q. Wu, and M. Pedram, “Maximum power estimation using the limiting distributions of extreme order statistics,” in Proc. Design Automation Conference, June 1998, pp. 684–689. Q. Qiu, Q. Wu, and M. Pedram, “Maximum power estimation using the limiting distributions of extreme order statistics,” in Proc. Design Automation Conference, June 1998, pp. 684–689. Q.Wu, Q. Qiu, and M. Pedram, “Estimation of Peak Power Dissipation in VLSI Circuits Using the Limiting Distributions of Extreme Order Statistics,” IEEE transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 20, no. 8, p Q.Wu, Q. Qiu, and M. Pedram, “Estimation of Peak Power Dissipation in VLSI Circuits Using the Limiting Distributions of Extreme Order Statistics,” IEEE transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 20, no. 8, p Copyright Agrawal, 2009ELEC / Spr 09, Lecture 634