ECE 7502 Project Final Presentation

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Presentation transcript:

ECE 7502 Project Final Presentation Effective IDDQ Testing method to identify the fault in Low-Voltage CMOS Circuits ECE 7502 Project Final Presentation W.P Manula Pathirana 21st April 2015

Design and Test Development Customer Requirements Validate Verify Specification Architecture PCB Architecture Design and Test Development Verify Logic / Circuits PCB Circuits Physical Design PCB Physical Design Test Fabrication PCB Fabrication Manufacturing Test Test Packaging Test PCB Test System Test

IDDQ flowing through inverter with and without defect[1] What is IDDQ testing? IDDQ testing is simple method to identify the defects on IC based on the steady state power-supply current. IDDQ(Measured)>IDDQ(Th) Defective IDDQ flowing through inverter with and without defect[1]

Problem statement Test escapes and yield loss IDDQ(Fault Free)≈IDDQ(Defective) Higher Leakage Low threshold Transistors For new Technologies (Deep submicron levels) Earlier Technologies[1] Deep submicron Technologies[1] [1]S. Sabade and D. M. Walker, “I DDX-based test methods: A survey,” ACM Trans. Des. Autom. Electron. Syst. TODAES, vol. 9, no. 2, pp. 159–198, 2004. A-test escapes B-yield loss

ΔIDDQ(Faulty)<<IDDQ(Defect free) Proposed Method IDDQ versus Temperature[2] ΔIDDQ(Faulty)<<IDDQ(Defect free) Low temperature measurement is undesirable in production due to high cost [2]A. Kaltchenko and O. Semenov, “Temperature dependence of IDDQ distribution: application for thermal delta IDDQ testing,” IET Circuits, Devices & Systems, vol. 1, no. 6, p. 509, 2007.

ΔIDDQ(Faulty)>> ∆IDDQ(Defect free) Proposed Method Expected out come ΔIDDQ(Faulty)>> ∆IDDQ(Defect free)

Proposed method Estimate IDDQ distribution at V1 for an inverter V2 >> V1 Estimate IDDQ distribution with artificially introduced faults at V1 and V2 for a simple inverter. Each resistive path is injected with a resistor to the circuit under test Intragate shorts(happen within a CMOS gate) Determine the V1,V2 and faults resistor values Extend the proposed method from inverter to 1-bit adder Explore the dependency of voltage delta IDDQ testing method on input logic using 1-bit adder Extend the proposed method to 100-bit adder circuit.

Result Fault can only be identified with current monitoring techniques Fault resistance value can be chosen as 5 kΩ The inverter Wp/Wn ratio is 432µm/236µm

Monte Carlo simulation on inverter at different voltages Result Test escape Yield loss Ith Monte Carlo simulation on inverter at different voltages

Result(voltage delta IDDQ testing) The proposed method uses two samples. A lot –Faulty circuit (Inverter with source drain short (Fault strength is 5kΩ) B lot –Fault Free circuit Monte Carlo simulation on Faulty Circuit at 0.1 V, 0.2 V and 0.25 V

Result(voltage delta IDDQ testing) The proposed method uses two samples. A lot –Faulty circuit (Inverter with source drain short (Fault strength is 5kΩ) B lot –Fault Free circuit Monte Carlo simulation on Faulty Free Circuit at 0.1 V, 0.2 V and 0.25 V

Result(voltage delta IDDQ testing vs. Thermal delta IDDQ) No overlapping Illustration of voltage delta IDDQ testing Illustration of temperature delta IDDQ testing

Result(voltage delta IDDQ testing)(1-bit adder) Fault free circuit Faulty circuit

Result(voltage delta IDDQ testing)(1-bit adder)(A=B=Cin= 1)

Result(voltage delta IDDQ testing)(1-bit adder)(A=B=0,Cin= 1)

Result(voltage delta IDDQ testing)(1-bit adder)(A=Cin= 1,B=0)

Result(voltage delta IDDQ testing)(1-bit adder)(A=0,B=Cin= 1) Still ∆IDDQFaulty>> ∆IDDQFaultFree where ∆IDDQFaulty=1.3x10-6 A and ∆IDDQFaultFree = 5x10-7 A

Result(voltage delta IDDQ testing)(100-bit adder) )(A=B=Cin= 1)

Conclusion Voltage delta IDDQ testing method is introduced. The method is implemented on inverter,1-bit adder and 100-bit adder circuit. By looking at ∆IDDQ on different voltage defected chip can be identified.(Usually ∆IDDQFaulty>> ∆IDDQFaultFree)

References [1] . S. Sabade and D. M. Walker, “I DDX-based test methods: A survey,” ACM Trans. Des. Autom. Electron. Syst. TODAES, vol. 9, no. 2, pp. 159–198, 2004. [2]. A. Kaltchenko and O. Semenov, “Temperature dependence of IDDQ distribution: application for thermal delta IDDQ testing,” IET Circuits, Devices & Systems, vol. 1, no. 6, p. 509, 2007. [3]. A. Abdollahi, F. Fallah, and M. Pedram, “Leakage current reduction in CMOS VLSI circuits by input vector control,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 140–154, Feb. 2004. [4]. Z. Chen, L. Wei, and K. Roy, “On effective I/sub DDQ/testing of low-voltage CMOS circuits using leakage control techniques,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 9, no. 5, pp. 718–725, 2001. [5].M. Karmani, C. Khedhiri, and B. Hamdi, “Design and test challenges in Nano-scale analog and mixed CMOS technology,” International Journal of VLSI design & Communication Systems (VLSICS) Vol, vol. 2, 2011.