PRAVEEN VENKATARAMANI VISHWANI D. AGRAWAL Auburn University, Dept. of ECE Auburn, AL 36849, USA 26 th International.

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Presentation transcript:

PRAVEEN VENKATARAMANI VISHWANI D. AGRAWAL Auburn University, Dept. of ECE Auburn, AL 36849, USA 26 th International Conference on VLSI Design Pune, India, January 7, 2013 Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage

Outline Introduction Problem statement Effects of reducing power supply Power and structure constrained tests Analyzing power constrained test Analyzing structure constrained test Finding an optimum test voltage Results Conclusion 1/7/2013 VLSI Design"2012 2

Introduction Signal transitions of scan ATPG patterns are higher than those of functional patterns  Cause high power dissipation during scan shift and capture  Peak power dissipation - IR drop failures  Average power dissipation – Excessive heating Power Constraint Test  Limit the maximum scan test cycle power to the allowable peak power  Slow down clock  Generate or modify vector and scan structure to reduce activity  Increased test time 1/7/2013 VLSI Design"2012 3

Problem Statement Limit maximum test power to the allowable peak power Reduce scan test time Proposed methodology  Reduce supply voltage to reduce power dissipation during test  Increase test clock frequency such that power dissipation meets the specification  Find the optimum voltage that allows the maximum power- constrained clock frequency for test 1/7/2013 VLSI Design"2012 4

Reducing Supply Voltage Advantages  Reduced test time  Certain defects are more profound at lower voltages  Resistive bridge fault  Power supply noise reduces Concerns to be investigated in the future  Increased the critical path delay  Possible changes in critical paths 1/7/2013 VLSI Design"2012 5

Power and Structure Constrained Tests Power Constraint  Scan based test power dissipation can be more than functional power dissipation  The maximum power dissipated by the test is limited by the maximum allowable power for the test.  Maximum activity test cycle determines the test clock frequency Structure Constraint  Clock frequency is determined by the critical path delay  Fastest test/functional clock period cannot be smaller than the critical path delay to avoid timing violation  Test at lower voltages tends to become structure constrained Trade Off  Slower clock ⇒ Less power ⇒ Longer test time  Faster clock ⇒ Higher power ⇒ Shorter test time 1/7/2013 VLSI Design"2012 6

Power and Structure Constrained Tests Courtesy: ITC Elevator Talk Reduced Voltage Test Can be Faster! by Vishwani AgrawalReduced Voltage Test Can be Faster! by Vishwani Agrawal 1/7/2013 VLSI Design"2012 7

Analysis of Power constrained test 1/7/2013 VLSI Design"2012 8

Analysis of Power constrained test 1/7/2013 VLSI Design"2012 9

Analysis of Structure Constrained Test 1/7/2013 VLSI Design"

Analysis of Structure Constrained Test Assumptions:  Critical path does not change as voltage is reduced; found valid for small voltage changes  Threshold voltage remains constant 1/7/2013 VLSI Design"

Analysis of Structure Constrained Test 1/7/2013 VLSI Design"

Optimum Test Time 1/7/2013 VLSI Design"

Optimum Test Time 1/7/2013 VLSI Design"

Results: Test Time Optimization CUT No. of Vec tors Scan cycles Peak power (µW) Nominal Voltage, 1.8V Optimum Voltage Test Time Reduc tion (%) Test freq. MHz Test Time (µs) Supply Voltage (volts) Test Freq. (MHz) Test Time (µs) s s s s s s s s /7/2013 VLSI Design"

Conclusion What we have achieved  Optimum test time for power constrained test  Optimum voltage and frequency for power constrained tests Future explorations  Consideration of separate critical paths for scan and functional logic  Delay testing at reduced voltage  Adaptive dynamic power supply  Dynamic test frequency (asynchronous testing) 1/7/2013 VLSI Design"