1 Some Limits of Power Delivery in the Multicore Era Runjie Zhang, Brett H. Meyer, Wei Huang, Kevin Skadron and Mircea R. Stan University of Virginia, McGill University, IBM Austin Research Lab.

ITRS Projection on Transistor Density (2011 Edition) 2 Source: ITRS 2011

Power Density and Current Density 3 A/mm 2 Current = Power / Supply Voltage

The Chip - Package 4 Source: pcgameshardware.com

5 The Chip – Inside the Package Source: ITRS 2009Edition,

The Chip – C4 Bumps Source: flipchips.com, Source: Wikipedia

What are the problems? 7 Year Total Pad Count Source: ITRS 2011Edition, Source: Shao et al. IEEE Computer Society Annual Symposium on VLSI, 2005 Source: Ye et al. Applied Physics letters, 2003 Electromigration

Architecture Level PDN Model 8

Input: –PDN physical parameters. E.g. metal width –Processor floorplan and powermap. –Pad configuration Output: –Voltage pad –Pad current 9 Architecture Level PDN Model

Validation 10 IBM Power Grid analysis benchmarks –Steady-State –SPICE format –Provides details about metal layer and Pad locations

11 Power Map VDD Pad Distribution IBM_PG6

Validation Results 12

Pad Current Comparison 13

Multicore Scaling 14 Baseline: 3.7GHz, Duo Core, Intel Penryn 4-way OoO Processor Private L2 cache, 3MB per core Mesh-Based NoC 45nm32nm22nm16nm # of Cores24816 Area(mm2) Supply Voltage Peak Total Power (W) Peak Total Current(A)

Flooplan 15

Power Delivery Noise Scaling Trend 16

Pad Optimization 17

18 Sorted Pad Current After Optimization Sorted Pad Current Before Optimization

I/O vs. Power Supply 19 Const core-to-MC ratio 80 pads per MC 5% IR drop target

Thermal vs. Power Delivery 20

Conclusions Power delivery is becoming a limiting factor in near future; IR drop poses a bigger challenge than ElectroMigration; Memory bandwidth will be affected’ With liquid cooling, scaling hit power delivery wall before thermal wall. 21

Questions? 22

Thanks! 23

Temerature Map vs. Voltage Map 24 Voltage (V) Temperature( o C)

25 Voltage (V) Temperature( o C)