Ethernet Driver Changes for NET+OS V5.1. Design Changes Resides in bsp\devices\ethernet directory. Source code broken into more C files. Native driver.

Slides:



Advertisements
Similar presentations
Question Bank. Explain the syntax of if else statement? Define Union Define global and local variables with example Concept of recursion with example.
Advertisements

Device Layer and Device Drivers
Device Drivers. Linux Device Drivers Linux supports three types of hardware device: character, block and network –character devices: R/W without buffering.
CSNB324 Advanced Operating Systems 6: Device Management
purpose Search : automation methods for device driver development in IP-based embedded systems in order to achieve high reliability, productivity, reusability.
Dr. Rabie A. Ramadan Al-Azhar University Lecture 3
The 8051 Microcontroller Chapter 5 SERIAL PORT OPERATION.
Memory management.
ECE 526 – Network Processing Systems Design Software-based Protocol Processing Chapter 7: D. E. Comer.
Embedded Systems Programming Networking on the puppeteer.
CSE Fall Introduction - 1 What is an Embedded Systems  Its not a desktop system  Fixed or semi-fixed functionality (not user programmable)
1 I/O Management in Representative Operating Systems.
NS Training Hardware. System Controller Module.
Multicore Navigator: Queue Manager Subsystem (QMSS)
October 11, Firmware for USB 2.0 Ryan Augustin Netchip Technology, Inc
NET+OS 6.1 Training. BSP NET+OS 6.1 BSP Initialization Memory map New features Debugging Porting Issues.
1 CS503: Operating Systems Part 1: OS Interface Dongyan Xu Department of Computer Science Purdue University.
CS 6560 Operating System Design Lecture 13 Finish File Systems Block I/O Layer.
1 Computer System Overview Chapter 1. 2 n An Operating System makes the computing power available to users by controlling the hardware n Let us review.
Real-time Systems Lab, Computer Science and Engineering, ASU Linux Input Systems (ESP – Fall 2014) Computer Science & Engineering Department Arizona State.
DAT2343 Accessing Services Through Interrupts © Alan T. Pinck / Algonquin College; 2003.
LWIP TCP/IP Stack 김백규.
Contact Information Office: 225 Neville Hall Office Hours: Monday and Wednesday 12:00-1:00 and by appointment.
1-1 Embedded Network Interface (ENI) API Concepts Shared RAM vs. FIFO modes ENI API’s.
NETOS5.1 Training NS7520 Overview NETOS5.1 Overview BSP Changes BSP & Board Configurations Build File Changes for GHS Makefile Changes for GNU Linker Files.
1-1 NET+OS Software Group Flash API Multiple flash memory bank support New Flash API introduction Detailed Flash API Function presentation Supporting.
Processes and Threads CS550 Operating Systems. Processes and Threads These exist only at execution time They have fast state changes -> in memory and.
Interrupts By Ryan Morris. Overview ● I/O Paradigm ● Synchronization ● Polling ● Control and Status Registers ● Interrupt Driven I/O ● Importance of Interrupts.
CCNA 3 Week 4 Switching Concepts. Copyright © 2005 University of Bolton Introduction Lan design has moved away from using shared media, hubs and repeaters.
Device Drivers CPU I/O Interface Device Driver DEVICECONTROL OPERATIONSDATA TRANSFER OPERATIONS Disk Seek to Sector, Track, Cyl. Seek Home Position.
© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction Purpose  This training course provides an overview of the CPU architecture.
NS Training Hardware.
Renesas Technology America, Inc. Flash!. CPU Rewrite CPU-rewrite is a term that refers to an Renesas MCU’s ability to erase/program its own internal Flash.
2003 Dominic Swayne1 Microsoft Disk Operating System and PC DOS CS-550-1: Operating Systems Fall 2003 Dominic Swayne.
3.14 Work List IOC Core Channel Access. Changes to IOC Core Online add/delete of record instances Tool to support online add/delete OS independent layer.
Queues, Pipes and Sockets. QUEUE A structure with a series of data elements with the first element waiting for an operation Used when an element is not.
4P13 Week 3 Talking Points 1. Process State 2 Process Structure Catagories – Process identification: the PID and the parent PID – Signal state: signals.
Moving Arrays -- 1 Completion of ideas needed for a general and complete program Final concepts needed for Final Review for Final – Loop efficiency.
Intro  Scratchpad rings and queues.  First – In – Firs – Out (FIFO) data structure.  Rings are fixed-sized, circular FIFO.  Queues not fixed-size.
KeyStone SoC Training SRIO Demo: Board-to-Board Multicore Application Team.
RTX - 51 Objectives  Resources needed  Architecture  Components of RTX-51 - Task - Memory pools - Mail box - Signals.
1 Computer Systems II Introduction to Processes. 2 First Two Major Computer System Evolution Steps Led to the idea of multiprogramming (multiple concurrent.
Chapter 2 Process Management. 2 Objectives After finish this chapter, you will understand: the concept of a process. the process life cycle. process states.
Queue Manager and Scheduler on Intel IXP John DeHart Amy Freestone Fred Kuhns Sailesh Kumar.
Renesas Electronics America Inc. RX Ethernet Peripheral © 2011 Renesas Electronics America Inc. All rights reserved A Rev /16/2011.
WIFI design Guide based PW620-I b/g ----Hardware section Orin.Zhu August 31 st, 2007.
NET+OS 6.1 Training. GPIO APIs NET+OS 6.1 Signal Multiplexing System tradeoffs affecting pin count at design-time. –NS9750 unit cost reduced by conserving.
DMA Driver APIs DMA State Diagram Loading Driver and Opening Channel DMA Channel Attributes Loading Data to a Channel Unloading Data from a Channel.
Embedded Real-Time Systems Processing interrupts Lecturer Department University.
CSL DAT Adapter CSL 2.x DAT Reference Implementation on EDMA3 hardware using EDMA3 Low level driver.
1 Chapter 2: Operating-System Structures Services Interface provided to users & programmers –System calls (programmer access) –User level access to system.
Z IGBEE and OSAL Jaehoon Woo KNU RTLAB. KNU RTLAB.
1394 H/W and OHCI Gi-Hoon Jung. 2002/01/162 Agenda Overview of the VITANA board OHCILynx PCI-based Host Controller Overview of the OHCI Spec.
Homework Reading Machine Projects
Linux Kernel Development - Robert Love
Process concept.
HIBI_PE_DMA Example.
Homework Reading Machine Projects Labs
The PCI bus (Peripheral Component Interconnect ) is the most commonly used peripheral bus on desktops and bigger computers. higher-level bus architectures.
Process Synchronization and Communication
Threads and Locks.
Final Review CS144 Review Session 9 June 4, 2008 Derrick Isaacson
NET+OS 6.1 Training.
Baremetal C Programming for Embedded Systems
NetSilicon & Digi Confidential
Computer System Overview
Lecture Topics: 11/1 General Operating System Concepts Processes
Accessing Services Through Interrupts
Robocon 2007 Electronics Quickstart!
Who’s listening? Some experiments with an ‘echo’ service on our anchor-cluster’s local network of 82573L nic’s.
Presentation transcript:

Ethernet Driver Changes for NET+OS V5.1

Design Changes Resides in bsp\devices\ethernet directory. Source code broken into more C files. Native driver code is separated from the TCP/IP stack and the operating system. Global variables are combined in one structure. Added a transmit task.

Hardware related Changes Added support for NS7520 chip. Added transmitter lockup detection and reset. The driver supports multiple receive DMA channels. Mii.c identifies PHY address dynamically. Both MAC and EFE run in half-duplex.

Driver Header Files h\efe_def.h- Ethernet driver public API, and statistics bsp\mii.h- MII public API In bsp\devices\ethernet directory: eth.h- Internal Ethernet definitions

Driver C Files eth_init.c- Initialization routines eth_reset.c- Hardware initialization eth_dma.c- DMA related routines eth_isr.c- Interrupt service routines eth_mcast.c- Multicast routines

Driver C Files eth_recv.c- Receive task and related routines eth_send.c- Transmit task and related routines eth_watchdog.c – Code to reset receiver and transmitter lockups

Driver C Files eth_os.c- Code dependant on the OS eth_stack.c- Code dependant on the TCP/IP stack mii.c- MII routines

NS7520 Support NS7520 has a different MAC. Ethernet register addresses and layout have changed. Most of the chip revision support is in eth_reset.c and mii.c.

Transmitter Lockup Reset Reset function - eth_reset_tx The eth_tx_complete in the transmit thread detects the lockup condition. Lockup condition - transmit complete interrupt has not cleared the Full bit in the DMA buffer descriptor.

Half – Duplex operation Full duplex for EFE causes transmit under- runs, which cause transmitter lockups. MAC and EFE duplex is set to the same value. ETH_NEGOTIATE_100MB_FULLD is defined to 0 is mii.h.

Other MII changes MII tries to identify PHY on different addresses. After reading the status, mii.c clears the status bit in the MII Command Register, because NS7520 hardware does not do it.

Multiple receive DMA channels #define ETH_RX_CHANNELS 1 #define ETH_MAX_RXA_DESCRIPTORS 64 #define ETH_MAX_RXB_DESCRIPTORS 1 #define ETH_MAX_RXC_DESCRIPTORS 1 #define ETH_MAX_RXD_DESCRIPTORS 1 Change ETH_RX_CHANNELS and number of buffer descriptors for channels B, C, and D to run more than one receive channel.

Multiple receive DMA channels #define ETH_MAX_PACKET_LENGTH1518 #define ETH_RX_PACKET_SIZEA 64 #define ETH_RX_PACKET_SIZEB 128 #define ETH_RX_PACKET_SIZEC 256 #define ETH_RX_PACKET_SIZED ETH_MAX_PACKET_LENGTH Last DMA channel always receives maximum size packets. BSP is compiled to use 1 receive DMA channel

DMA Buffer Descriptors They are made global for debug purposes. DMA buffer descriptors are defined in eth_dma.c. / * Transmit DMA Buffer descriptor ring */ fb_buffer_desc_t eth_tx_buffer_descriptors[ETH_MAX_TX_DESCRIPTORS];

DMA Buffer Descriptors / * Receive DMA Buffer descriptors rings for channels A, B, C, and D */ fb_buffer_desc_t eth_rxa_buffer_descriptors[ETH_MAX_RXA_DESCRIPTORS]; fb_buffer_desc_t eth_rxb_buffer_descriptors[ETH_MAX_RXB_DESCRIPTORS]; fb_buffer_desc_t eth_rxc_buffer_descriptors[ETH_MAX_RXC_DESCRIPTORS]; fb_buffer_desc_t eth_rxd_buffer_descriptors[ETH_MAX_RXD_DESCRIPTORS];

DMA Buffer Descriptors /* Array Pointers to Receive DMA Buffer descriptor rings for channels A, B, C, and D */ fb_buffer_desc_t *eth_rx_buffer_descriptors[] = { eth_rxa_buffer_descriptors, eth_rxb_buffer_descriptors, eth_rxc_buffer_descriptors, eth_rxd_buffer_descriptors };

Sending Packets Packets are transmitted from application threads and the Ethernet transmit thread. TCP/IP stack owns device transmit queues. TCP/IP stack calls driver’s transmit routines in critical section.

Transmit Task Transmit DMA ISR wakes up the transmit thread. The transmit thread calls eth_restart in a loop. eth_restart calls a stack function to free the transmitted packet, and send the next queued packet.

eth.h eth.h explains what definitions are BSP configurable. eth.h defines ethData structure. Driver modules use and a global pointer: ethData *eth_datap.

typedef struct { void *pnetdev; /* pointer to TCP/IP stack device data */ unsigned int min_packet_len; /* minimum packet length */ unsigned int max_packet_len[ETH_RX_CHANNELS]; /*minimum packet length*/ char state; /* drive state */ char efe_mii_100; /* 1 = 100Mb, 0 = 10 Mb */ char mac_fulld; /* MAC is running full duplex */ char efe_fulld; /* EFE is running full duplex */ char pna_mode; /* TRUE = pNa mode is set */ char loopback; /* loopback mode */ char rx_reset_in_progress; /* receiver reset in progress */ int rx_bd_index[ETH_RX_CHANNELS]; /* Receive DMA software index */ int tx_bd_head; /* Transmit DMA head index */ int tx_bd_tail; /* Transmit DMA tail index */ char mac_addr[ETH_MAC_ADDR_SIZE]; /* MAC adddress */ ethFunction recv_task; /* receive task function pointer */ ethFunction xmit_task; /* transmit task function pointer */ ethFunction watchdog; /* watchdog function pointer */ } ethData;

eth_os.c eth_init_os_services allocates memory and creates threads, timers, event flags, etc. without starting them. eth_start_os_services starts threads, timers. eth_stop_os_services stops threads, timers. eth_task_wake wakes up a driver thread. eth_task_sleep suspends a driver thread until it’s waken up by eth_task_wake.

eth_stack.c Provides a glue layer between the driver and TCP/IP stack. The only file to include stack headers. Handles everything about struct m.