Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Advanced Computer Architecture Lecture 24 Eight-node distributed computer Ring router design

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Distributed computer No global or shared memory Interconnect P M... P M P M

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering System schematic Node

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Ring router block diagram In Out D In I/F Out I/F CPU I/F Latch Controller LatchDriver

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Ring router schematic (ROUTER.CKT) input buffer write buffer

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Router controller schematic 4 Inputs 9 Outputs FSM contains 4 inputs and 9 outputs

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Simplified state diagram 0 Write mode Read mode Pass mode Reset WReqRReq IReq Hint: each mode requires 4 states

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering RTRFSM state diagram 0000 dl e g kc hf ijab Reset WReq RReq IReq WReq RReq IReq OAck IReq OAck WBClk WBE OReq WAck IBClk IBE RBE RAck OReq IBClk IBE OReq IAck Reset IAck WBE OReq WReq IBE RBE RReq IReq IBE

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering PSRBEWBEWBClkIBEIBClkWAckRAckOReqIAck a b c d e f g h i j k l Find the output table?

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering FSM timing: write

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering FSM timing: read

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering FSM timing: pass

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Eight-node example Write Pass Read

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering System timing

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Message format Header: routing and control information Payload: data Trailer: error checking code (ECC) Header PayloadTrailer time

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Unidirectional ring router Ring Router IReq IAck In OReq OAck Out RReq WReq RAck WAck D Link inputLink output Processor

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for DMA interface?

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for header?

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for fixed length message?

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for trailer?

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for interference?

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering PSRBEWBEWBClkIBEIBClkWAckRAckOReqIAck a111 b10111 c1011 d1111 e111 f111 g0101 h01011 i111 j11011 k1101 l1111 Find the output table?

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for DMA interface? CPU writes a word count CPU writes a memory address CPU writes a start command CPU does other useful work DMA responds with interrupt CPU acknowledges interrupt CPU processes message

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for header? Router looks at first byte If destination address is to CPU, then routes data to processor port (buffer) If address is not to CPU, then passes data to correct link based on destination address

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for fixed length message? Header byte resets counter Each new byte processed decrements counter When counter zero, message complete

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for trailer? Each new data byte added to checksum calculation Calculated checksum compared to message checksum, error results in CPU interrupt

Spring EE 437 Lillevik 437s06-l24 University of Portland School of Engineering Changes for interference? Design must support all possible concurrency modes Router checks for interference Possible responses –Block a message (deadlock possible), requires arbitration algorithm –Time multiplex (n-way) the link