A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio Compound Semiconductor IC Symposium A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio Mehdi Khanpour+, Sorin Voinigescu+, M. T. Yang* +University of Toronto, *TSMC October 2007

Outline Motivation 60-GHz Radio PA schematic Fabrication Measurement results Conclusion October 2007 Mehdi Khanpour

Motivation 60-GHz Band (57-64 GHz) CMOS alternative Large bandwidth and limited propagation High data rate (4+Gbps), short range Personal Area Networks, Wireless HDTV CMOS alternative lower power higher integration and lower cost October 2007 Mehdi Khanpour

60-GHz Radio Simple narrow-band radio architecture Implemented in 90nm CMOS Receiver w/o VCO [1] Up-converter [2] Power Amplifier (this work) October 2007 Mehdi Khanpour

PA Schematic Input designed as LNA with inductive feedback Input matched by LG and LS Output designed as PA with source degeneration for linearity October 2007 Mehdi Khanpour

PA Design Stage 1 biased at 0.2 mA/μm and sized for simultaneous noise and input impedance matching Stage 2 and 3 biased at 0.3 mA/μm for linearity Output stage sized for PSAT = 6.5 dBm with Inductive degeneration for linearity Inductors and interconnects modeled using ASITIC October 2007 Mehdi Khanpour

Fabrication Fabricated in TSMC 90nm GP CMOS 9-layer Cu back-end, no “thick” metal Large signal test setup: 67GHz Cable 110GHz Cable 67GHz Infinity Probes 50GHz Bias T 300μm× 500μm October 2007 Mehdi Khanpour

Simulations 18 dB Gain, 4.5 dB NF Γopt, S11 and S22 < -10 dB from 50-68 GHz October 2007 Mehdi Khanpour

Measurement vs. Simulation 14 dB Gain, 3dB bandwidth extends from 48-61 GHz S11 and S22 < -10 dB from 48-65 GHz October 2007 Mehdi Khanpour

Measurement vs. Simulation Measurement shows 14 dB gain @ 55 GHz Diffusion region in layout is wider than the minimum allowed by design kit Extra capacitance pushing the centre frequency down is not captured in simulations October 2007 Mehdi Khanpour

Measurement vs. Simulation S21 peaks at 55 GHz when extra capacitance is added October 2007 Mehdi Khanpour

S-Parameters Across 5 Dies Results show excellent repeatability October 2007 Mehdi Khanpour

S21 vs. Power Supply 2 dB drop in gain from 1.5V to 1.2V supply October 2007 Mehdi Khanpour

Linearity Measurement 6 dBm PSAT, 1.6 dBm P1dB Maximum PAE is 6% @ 55 GHz and 5.2% @ 60 GHz, η = 22% October 2007 Mehdi Khanpour

Linearity vs. Current Density Optimal linearity bias coincides with peak fT current density of 0.3~0.35 mA/μm October 2007 Mehdi Khanpour

Temperature Measurements Gain decreases by 5 dB and PSAT by 2 dBm from 25oC to 100oC October 2007 Mehdi Khanpour

Scaling Same concept implemented in 65nm at 80 GHz Third stage is cascode with identical size (40 μm) Higher gain but lower PSAT due to cascode output stage, η = 11% October 2007 Mehdi Khanpour

200/290 GHz fT/fMAX SiGe HBT [4] 200/290 GHz fT/fMAX SiGe HBT [5] PA Comparison PA Technology f G PSAT P1dB,out PAE Area Topology FoM 170 GHz fMAX 90nm CMOS 60 GHz 14 dB 6 dBm 1.6 dBm 6% 0.3×0.5mm2 2-stage cascode + CS 10 170 GHz fMAX 90nm CMOS [3] 5.2 dB 9.3 dBm 6.4 dBm 7.4% 0.35×0.43mm2 3-stage CS 7.5 200/290 GHz fT/fMAX SiGe HBT [4] 10.8dB 16 dBm 11.2 dBm 4.3% 2.1×0.8mm2 2-stage CE 73 200/290 GHz fT/fMAX SiGe HBT [5] 77 GHz 19dB 14 dBm 12 dBm 15.7% NA cascode + 444 October 2007 Mehdi Khanpour

Conclusion 60-GHz PA with 14 dB gain demonstrated in 90nm CMOS PA characterized over process, supply voltage and temperature variation Results show excellent yield and repeatability Scalable to 80 GHz in 65nm CMOS October 2007 Mehdi Khanpour

Acknowledgment Jaro Pristupa and CMC for CAD tools and support OIT and CFI for equipment grants TSMC for facilitating the technology access October 2007 Mehdi Khanpour

References [1] D. Alldred et al, CSICS 2006 [2] S. P. Voinigescu et al, ISCAS 2007 [3] T. Yao et al. RFIC-Symp 2006 [4] B. Floyd et al, ISSCC 2004 [5] S. T. Nicolson et al, IMS 2007 October 2007 Mehdi Khanpour