The World Leader in High-Performance Signal Processing Solutions Design a Clock Distribution for a WCDMA Transceiver System CSNDSP 2006 Session: B.11 Systems - Simulators Presenter: Dimitrios Efstathiou July 20 th, 2006

2 In this presentation we will cover  Where we need Clock Distribution Devices?  Clock Design for a WCDMA Transceiver System  Introduction to ADIsimCLK TM  ADIsimCLK TM Results versus Lab measurements

3 Telecom Infrastructure ATM Based Network IP Core Network (IPv6, MPLS) ATM Based Network IP Core Network (IPv6, MPLS) 3G Macro 2G Macro

4 Solution to save cost, board space U3 Divide by 4 LVPECL U5 Delay 1-10ns LVPECL U1 1:4 Fanout BufferLVPECL U4 Divide by 8 LVPECL U7 LVPECL to CMOS U6 CMOS Integrated Circuit Solution in one small package FanoutDividers Delay Logic Translation U2 Divide by 2 LVPECL

5 Application – Wireless Transceiver Card Critical Clock Functions on Transceiver Card: clean-up jitter on user’s input reference up-convert user reference frequency to highest frequency needed, usually driven by DAC clock requirements generate multiple frequencies for Rx & Tx provide low jitter clocks for data converters generate mix of LVPECL, LVDS, CMOS clocks adjust phase or delay between clock channels offer isolation between clock channels ADC Transmitter/Receiver Clock Distribution IC ADC DDC or ASIC DAC DUC or FPGA DAC User’s Reference Clock Clock to A-D Converters Clock to D-A Converters Clock to Digital Chips TRX Cards

6 Transceiver clock design using ADIsimCLK™

7 A Clock Distribution Device with integrated PLL LF VCO

8 ADC Output clocked by AD9510 AD MHz DAC 1 DAC 2 AD6633 DUC LVPECL MHz I-channel Q-channel CMOS MHz AD9430 AD9445 AD6636 DDC LVPECL MHz AD MHz Auxilary temperature measurement ADC To reconstruction filters and modulator Receiver path from Mixer Carriers 1 & 2 OUT0 OUT7 OUT3 OUT4 OUT6 OUT2 CMOS MHz OUT5 FPGA DPD AD9779 Observation path down-converted from Power Amplifier Carriers 1 & 2 LVDS MHz LVPECL MHz LVDS MHz Carrier 1 I/Q Carrier 2 I/Q Rx Baseband Tx Baseband Real Imaginary OUT1 LVEPCL MHz Carrier 1 I/Q Carrier 2 I/Q

9 DAC Output clocked by AD9510

10 ADIsimCLK™ ADIsimCLK is a powerful and flexible tool. It can help a user design high performance clocking systems using low-jitter clock chips. ADIsimCLK phase noise simulations match the product information sheet typical values within ~2 dB. Timing simulations align well with product information sheet typical values.

11 Select the ADI clock chip: AD9510 specs Clock Device see product information sheet

12 Select the configuration: Use integrated PLL Default Configuration Use integrated PLL Use external filter Use clock distribution circuit only

13 VCO Selection: VCO library see product information sheet

14 PLL Loop Filter Selection: Passive and active filters Loop bandwidth and phase margin

15 Clock Distribution Configuration: Enable Outputs Eight clock outputs Configuration per output

16 Clock Distribution Configuration: Configure Output Integration Interval Divider value Output Freq.

17 Results Page: OUT2 (LVPECL)

18 Another Design Example: Clock Distribution circuit only

19 ADIsimCLK versus Lab measurements

20 In summary we discussed  A Clock Design Strategy for a WCDMA Transceiver System  ADIsimCLK TM: A Clock generation and distribution simulator  Download this free tool at Thank you!

21 PLL Frequency Set-up: PLL Frequency PFD Frequency

22 Input Clock Selection: Choose an input Reference frequency.

23 Information on the PLL: Frequency Domain

24 Phase noise and timing jitter at a divider’s input and output Root mean square (rms) value of integrated phase noise (units in radians) Transition of a divider’s output is re-sampled with a transition of its input, a jitter of value Tjitter occurring at the input will cause the same amount of jitter at the output.

25 Get the results: schematic

26 Get the results: text report

27 Get the results: timing 0.11 ns