Introduction to IC Fabrication Semiconductor Process Technology io Lecture 1 Introduction to IC Fabrication School of Microelectronic Engineering

Semiconductor Process Technology HISTORY School of Microelectronic Engineering

Semiconductor Process Technology What is Semiconductor Process Technology? The technology to produce IC microchips IC chips are the backbone of the computer industry and have spurred related technologies such as software and internet Every product of the information age is an offspring of IC technology IC chips increasingly control functions in cars, TVs, VCRs, cameras, mobile phones, toys, etc. The current technology is as a result of years of research and development, taken many thousands of scientists, engineers and technicians. ` School of Microelectronic Engineering

Semiconductor Process Technology The Evolution of IC ` School of Microelectronic Engineering

Semiconductor Process Technology First Transistor, Bell Lab 1947 John Bardeen and Walter Brattain, demonstrated a solid state device made from germanium. They observed that when electrical signals were applied to contacts on germanium, the output power was larger than the input. These results were published In 1948. William Shockley, found out how the bipolar transistor functioned and published the theory in 1949. Three of them shared the Nobel Prize in physics in 1956, School of Microelectronic Engineering

Semiconductor Process Technology First Transistor and Its Inventors ` School of Microelectronic Engineering

Semiconductor Process Technology Semiconductor industry developed rapidly and germanium based transistor quickly replaced vacuum tubes in electronics equipment due to: smaller size lower power consumption lower operating temperature quicker response time Single crystal silicon and germanium based devices introduced in 1950 and 1952 respectively (better defect control, hence higher yield). School of Microelectronic Engineering

Semiconductor Process Technology Shockley left Bell Labs in 1956, to start his own lab in San Francisco Bay, California. Nowadays known as Silicon Valley. His lab has attracted talented scientist such as Robert Noyce and Gordon Moore. Gordon Moore and Robert Noyce left Shockley in 1957 to start Fairchild Semiconductor. School of Microelectronic Engineering

Semiconductor Process Technology First IC Device by Jack Kilby, Texas Instruments 1958 1st fabricated by Bell Labs in 1958. Jack Kilby demonstrated functional IC, fabricated on germanium strip consists of; one transistor one capacitor 3 resistors ` School of Microelectronic Engineering

Semiconductor Process Technology First Silicon IC Chip by Robert Noyce, Fairchild Camera, 1961 Fairchild Semiconductor produced the 1st commercial ICs in 1961. This IC consists of only 4 transistors sold for USD 150 a piece. NASA was the main customer. In 1968, Robert Noyce cofounded Intel Corp. with Andrew Groove and Gordon Moore. ` School of Microelectronic Engineering

Semiconductor Process Technology Moore’s Law ` School of Microelectronic Engineering

Semiconductor Process Technology Moore’s Law, Intel Product ` School of Microelectronic Engineering

Semiconductor Process Technology IC Integration Scale ` School of Microelectronic Engineering

Semiconductor Process Technology Feature Size and Wafer Size ` School of Microelectronic Engineering

Semiconductor Process Technology Road Map Semiconductor Industry ` School of Microelectronic Engineering

Semiconductor Process Technology Limit of IC Size Is there a limit for the minimum feature size? ` School of Microelectronic Engineering

Semiconductor Process Technology Limit of IC Device ` School of Microelectronic Engineering

Semiconductor Process Technology IC Product Category ` School of Microelectronic Engineering

Semiconductor Process Technology ` OVERVIEW ON IC MANUFACTURING School of Microelectronic Engineering

Semiconductor Process Technology IC Manufacturing A very complicated process, involves; Circuit design Manufacturing material Clean room technology, processing, equipment Wafer processing technology Die testing Chip packaging and final test ` School of Microelectronic Engineering

Semiconductor Process Technology IC Manufacturing Flow Design Mask info to MASK-SHOP + GDSII file Mask making Generate runcard Wafer Preparation Front-end Processes (individual transistor) Deposition Oxidation Diffusion Photolithography Etch (wet and dry) Implantation Backend Process Deposition (oxide, nitride etc) Metalization Rapid Thermal Process Lithography & Etch Test (Parametric and Functional) Packaging Final Test School of Microelectronic Engineering

Semiconductor Process Technology IC Manufacturing Processes School of Microelectronic Engineering

Semiconductor Process Technology IC Manufacturing Processes School of Microelectronic Engineering

Semiconductor Process Technology IC Design: Idea to Design Synthesis ` School of Microelectronic Engineering

Semiconductor Process Technology IC Design: Architecture to Layout ` School of Microelectronic Engineering

Semiconductor Process Technology Architectural Design – Defines the application operating system and devides modules for system. SDA GND A2 A0 A1 SCL WP VCC Charge Pump 16K-bits Memory Cell Timer Control Logic (Master) EEPROM Design Layout E/W circuit Decoder Xe Decoder Xr Dec Y Data ctrl Address block Decoder px ` School of Microelectronic Engineering

Semiconductor Process Technology Logic Design – Puts logic units such as adders, gates, inverters and registers into each module and run subroutines in each module . Circuit / Transistor Design – Individual transistors are laid out in each logic unit. Layout – To transfer from schematic to layout pMOS nMOS VDD VSS S D VIN VOUT School of Microelectronic Engineering

Semiconductor Process Technology IC Design: Design Flow ` School of Microelectronic Engineering

Semiconductor Process Technology Wafer Fabrication: From Design to Wafer ` School of Microelectronic Engineering

Semiconductor Process Technology IC Design: 1st IC 1st IC design by hand (Jack Kilby) Currently, hundreds of designers work on single product to design, validate and lay outed will take several months to complete with the help of CAD tools. Main considerations; performance die size design time and cost testability ` School of Microelectronic Engineering

Semiconductor Process Technology IC Design: State of The Art IC CMOS Inverter - basic building block of digital MOS design Layout Cross section School of Microelectronic Engineering

Semiconductor Process Technology IC Design: Layout and Mask s of CMOS Inverter School of Microelectronic Engineering

Semiconductor Process Technology Mask / Reticle After IC design is completed, generated layout image is printed on a piece of quartz glass coated with a layer of chromium. A laser beam projects the layout image onto the photoresist coated chrome glass surface. Photon change the chemistry of the exposed photoresist via a photo chemical reaction, and later dissolved in a base developer solution. A pattern etching removes the chromium at the exposed area. Therefore, it transfers the image of the IC layout to the quartz glass. This is done at mask shop School of Microelectronic Engineering

Semiconductor Process Technology Mask / Reticle Mask – Covers the whole wafer, used in projection, proximity and contact lithography technique. Reticle – Covers only part of the wafer, employed in step and repeat MASK RETICLE School of Microelectronic Engineering

Semiconductor Process Technology Typical Wafer Fabrication Process Flow Around 500 process steps to complete IC fabrication Involves 20 masking steps School of Microelectronic Engineering

Semiconductor Process Technology OVERVIEW ON WAFER FABRICATION School of Microelectronic Engineering

Semiconductor Process Technology Wafer Fabrication Objectives School of Microelectronic Engineering

Semiconductor Process Technology Why Yield Is Important? School of Microelectronic Engineering

Semiconductor Process Technology Wafer Yield The ratio between number of good wafers after finishing all the process steps, and total number of starting wafers . School of Microelectronic Engineering

Semiconductor Process Technology Die Yield The ratio between number of good dies per total of dies on the tested wafer after functional probe test. School of Microelectronic Engineering

Semiconductor Process Technology Packaging Yield The ratio between number of good chips after finishing all the packaging steps, and total of chips packaged. School of Microelectronic Engineering

Semiconductor Process Technology Overall Yield Wafer yield depends mainly on processing and wafer handling. Careless handling and robot malfunction could break wafers Faulty process such as misaligned during lithography, large amount of particles, poor process uniformity, etc can also ruin wafers. School of Microelectronic Engineering

Semiconductor Process Technology How Does Fab Make Money School of Microelectronic Engineering

Semiconductor Process Technology How Does Fab Make (Loss) Money School of Microelectronic Engineering

Semiconductor Process Technology Defects and Yield Y – overall yield D – defect density (minimum level determined by facilities) A – chip area (die size) n – number of processing steps School of Microelectronic Engineering

Semiconductor Process Technology Yield and Die Size School of Microelectronic Engineering

Semiconductor Process Technology Yield Curve School of Microelectronic Engineering

Semiconductor Process Technology Typical Production Wafer School of Microelectronic Engineering

Semiconductor Process Technology Typical Production Wafer School of Microelectronic Engineering

Semiconductor Process Technology Why Cleanroom ? School of Microelectronic Engineering

Semiconductor Process Technology Cleanroom School of Microelectronic Engineering

Semiconductor Process Technology Cleanroom Class School of Microelectronic Engineering

Semiconductor Process Technology Cleanroom Class School of Microelectronic Engineering

Semiconductor Process Technology Cleanroom Class (Definition of Airborne Particulate) School of Microelectronic Engineering

Semiconductor Process Technology Effect of Particles on Mask School of Microelectronic Engineering

Semiconductor Process Technology Effect of Particles on Wafer School of Microelectronic Engineering

Semiconductor Process Technology Cleanroom Structure Main features; raised floor laminar air flow HEPA filters higher pressure controlled humidity and temperature School of Microelectronic Engineering

Semiconductor Process Technology Gowning Area School of Microelectronic Engineering

Semiconductor Process Technology Typical Wafer Process Flow School of Microelectronic Engineering

Semiconductor Process Technology Typical Wafer Process Flow School of Microelectronic Engineering

Semiconductor Process Technology Typical Process Bay School of Microelectronic Engineering

Semiconductor Process Technology Wafer Test Parametric Test (Wafer Acceptance Test Data) Functional Test (Die Yield) School of Microelectronic Engineering

Semiconductor Process Technology Device Specifications (Transistor) School of Microelectronic Engineering

Semiconductor Process Technology Device Specifications (Resistance) School of Microelectronic Engineering

Semiconductor Process Technology Parametric Test Result (WAT Data) School of Microelectronic Engineering

Semiconductor Process Technology Functional Test School of Microelectronic Engineering

Semiconductor Process Technology Packaging 4 Main Purposes; to provide physical protection for the IC chip to provide a barrier layer against chemical impurities and moisture to connect the IC chip to the electrical circuit board to dissipate heat generated during chip operations School of Microelectronic Engineering

Semiconductor Process Technology Main Packaging Steps Wafers coated with protective layers on the surface, mechanically polished on the wafer backside to reduce thickness (600 to 300 um) A thin layer of gold is coated at the wafer backside Protective layer at the wafer surface is removed, and wafer backside is taped to on a solid frame. Then wafer sawing process. Die sorting (to pick up good dies) Die attach (to attach good dies to a packaging socket) Wire bonding School of Microelectronic Engineering

Semiconductor Process Technology Chip Bond Structure School of Microelectronic Engineering

Semiconductor Process Technology Wire Bonding School of Microelectronic Engineering

Semiconductor Process Technology Wire Bonding School of Microelectronic Engineering

Semiconductor Process Technology IC with Bonding Pads School of Microelectronic Engineering

Semiconductor Process Technology IC Chip Packaging School of Microelectronic Engineering

Semiconductor Process Technology Chip with Bumps School of Microelectronic Engineering

Semiconductor Process Technology Flip Chip Packaging School of Microelectronic Engineering

Semiconductor Process Technology Bump Contact School of Microelectronic Engineering

Semiconductor Process Technology Heating and Bumps Melt School of Microelectronic Engineering

Semiconductor Process Technology Molding Cavity for Plastic Packaging School of Microelectronic Engineering

Semiconductor Process Technology Ceramic Seal School of Microelectronic Engineering