Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths Nicola Nicolici and Bashir M. Al-Hashimi

Purpose Investigate power dissipation during testing Propose novel power conscious –Test synthesis algorithms –Test scheduling algorithms

Outline Motivation Built-in self-test (BIST) –Register-transfer level (RTL) data paths Power dissipation classification Power conscious design space exploration: –Test synthesis –Test scheduling Experimental results Conclusion

Motivation Low power synthesis assumptions –Primary input transition probabilities –State transition probabilities High power dissipation during testing –High temperature => reliability decrease –Power/ground noise => yield loss

Motivation (cont) S1 S2S5 C S S3S4 State Code S1 000 S2 011 S3 001 S4 010 S Functional Transitions transition nt scan sequential circuit transition nt Scan Transitions Shift out S5=100 Shift in S4=010 NO correlation PROBLEM!

Motivation (cont) Scan BIST environment –Test vector inhibiting techniques –Modified scan cell design –Low transition test pattern generator Standard scan design for test (DFT) –Test vector / scan latch ordering –Extra primary input vectors –New test application strategies

Motivation (cont) * *2 +1 v1 v2 v3v4v5v6 v7v8v9 v10 v11v12 v13 Register Variables R1 v1,v11 R2 v2,v12 R3 v7 R4 v5 R5 v6, v8 R6 v3 R7 v9 R8 v4,v10,v13 Clock 1 Clock 2 Clock 3 Clock 4 Clock 5

Motivation (cont) R1 * R2 R3 R4 R5 R6 R7 R8 + - Clock 1 and 4 Clock 2 and 3 Clock 2 Clock 3 Note: R8 and – are active in clock 5

BIST for RTL data paths Library HDL RTL synthesis netlist layout logic optimization layout synthesis BIST structures: LFSR MISR BILBO CBILBO + test controller

BIST for RTL data paths (cont) Test register allocation determines test schedule LFSR2 M1M2M1M2 T1T2 T1 T2 INTERRELATION NEEDS TO BE CONSIDERED! Previous power conscious test scheduling – No relation: test scheduling and test synthesis R1 LFSR2LFSR1

Power dissipation classification According to necessity for test efficiency –Necessary power dissipation –Useless power dissipation According to occurrence during testing –Test application power dissipation –Shifting power dissipation

Power dissipation classification (cont) Previous test scheduling approaches assume: – fixed amount of power for each module – not applicable to BIST RTL data paths C0C1 MISR0 R2 MISR1 Necessary power Useless power Inactive resources +0+1

Power conscious exploration Novel power conscious test synthesis Novel power conscious test scheduling Exploration strategies using tabu search –Time and Area oriented – TA-TSS –Power Conscious oriented – PC-TSS

R1 +0 LFSR0 +1 LFSR2 +2 LFSR1 +0 LFSR0 +1 R2 +2 useless power elimination Necessary power Useless power Inactive resources Power conscious exploration (cont) TEST SYNTHESIS

useless power elimination R3R R3R4 Necessary power Useless power Inactive resources Power conscious exploration (cont) TEST SCHEDULING

Power conscious exploration (cont) 2 test sessions: 1 for multiplier *, 1 for ALUs (+,-) R1 * R2 R3 R4 R5 R6 R7 R8 + -

Power conscious exploration (cont) BILBO1 * BILBO2 R3 LFSR4 LFSR7 BILBO8 +- C+ C- C1C2 C8 TA-TSS – test session 1 LFSR5 R6 Necessary power Useless power Inactive resources

Power conscious exploration (cont) LFSR1 * LFSR2 MISR3 LFSR4 LFSR5 BILBO6 MISR7 LFSR8 +- C+ C- C1C2 C8 PC-TSS – test session 1 Necessary power Useless power Inactive resources

Power conscious exploration (cont) BILBO1 * BILBO2 R3 LFSR4 LFSR7 BILBO8 +- C+ C- C1C2 C8 TA-TSS – test session 2 LFSR5 R6 Necessary power Useless power Inactive resources

Power conscious exploration (cont) LFSR1 * LFSR2 MISR3 LFSR4 LFSR5 BILBO6 MISR7 LFSR8 +- C+ C- C1C2 C8 PC-TSS – test session 2 Necessary power Useless power Inactive resources

Experimental results

Experimental results (cont)

Conclusion Testable design space exploration –Interrelation: test synthesis and scheduling –Variable power dissipation for each test Novel algorithms –Power conscious test synthesis –Power conscious test scheduling Ongoing and future work –Test controller: optimise area / performance –2 chips design and manufacturing