Reducing Synchronization Overhead in Test Data Compression Environments Paul Theo Gonciari Bashir Al-Hashimi Electronic Systems Design Group University of Southampton, UK Nicola Nicolici Electrical and Computer Engineering McMaster University, Canada

Overview TDCE and synchronization issues –Generic on-chip decoder –Synchronization overhead in TDCE Previous solutions –Tailoring the compression method –Interleaving architecture Proposed solutions –Tailoring the compressed test set –Distribution architecture Experimental results Conclusions

Test data compression Exponential increase in volume of test data (ITRS) 60% of ATE upgrade caused by memory (EETimes) Solutions Built-in self-test (BIST) Test data reduction –Useless – UMA [Gonciari et. al, VTS02] –Useful – test data compression TDCE [Gonciari et. al, DATE02] On-Chip Decoder ATE SOC CUT uncompressed compressed

Generic on-chip decoder Serial decoder –PG and CI can not work independently –Implicit communication between PG and CI Parallel decoder –PG and CI can work independently –Explicit communication between PG and CI

Synchronization overhead - Serial decoder De-serialization unit Multiple ATE channels and FIFO-like structure Synchronization channels necessary

Synchronization overhead - Parallel decoder NO De-serialization unit Single ATE channel and FIFO-like structure Synchronization channels necessary

Previous solution – Serial decoder Interleaving architecture [Chandra et. al, TCAD01] –Single channel FIFO-like structure –Synchronization channels –Interleaving FSM –Changes serial-decoders to ease the control –Does not exploit frequency ratio

Previous solution – Parallel decoder Tailoring the compression method [Jas et. al, VTS99] –Decoder dependent on frequency ratio –Imposes ATE restrictions –Changes the on-chip decoder –NO FIFO-like structure needed –NO interleaving FSM

Proposed core level solution Tailoring the compressed test set –Applicable when FIFO-like structures are needed –Insert dummy bits –FIFO-like structure is eliminated –NO changes to on-chip decoders –Decoder independent of the frequency ratio t cmp = stop 1 stop t cmp = D 1D

Proposed system level solution Distribution architecture SOC

Distribution architecture Composite test set –Tailor compressed test sets –Simple merge procedure NO changes to on-chip decoders Easy design integration for TDC system test Applicable to any parallel decoder Applicable to LFSR architectures when reseeding IEEE compatible solution for SOC TDC test Reduces trade-off

cmp vs. set – s38417 (

cmp vs. set vs. distr – S1

inter vs. distr – S2

Conclusions Synchronization overhead in TDCE Proposed two solutions –Core level solution Tailor the compressed test set –System level solution Distribution architecture IEEE compatible solution for SOC TDC test Future work –Integrate TDC in system level design flow

Example – VIHC [Gonciari DATE02] Core level solution t cmp = stop 1 stop t cmp = D 1D