Petros OikonomakosMark Zwolinski Controller Self-checking in a Controller / Datapath Architecture Electronics and Computer Science University of Southampton, UK Electronic Systems Design Group 3 rd UK ACM SIGDA Workshop on EDA Southampton, UK, September 2003

Outline Introduction Target Architecture Parity-based Techniques Intrinsically Secure States Self-checking design theory 1/n self-checking Conclusion

Introduction Starting point : controller / datapath system, self- checking datapath [Oikonomakos et al, DATE 2003] Goal : controller self-checking, integration with previous work Requirements : technology independence, ease of automation (time to market), area efficiency, adherence to self-checking theory Complete, automatically produced, controller / datapath self-checking solution!!!

Target Architecture Controller / datapath architecture Possibly several communicating FSMs Previous work : self-checking at point A Self-checking at point B is essential!!!

Per process parity-based self-checking

Single parity-based self-checking

per process parity checking : ~(N S +5×n) gates single checker : ~N S gates N S : total number of states n : number of processes the higher the degree of parallelism, the more the hardware savings!!! Hardware Costs

Intrinsically Secure (I.S.) States

Exploiting I.S. States in a process basic scheme detects all single control signal faults possibly little hardware saving several multiple faults are also detected!!!

Per process I.S. states-based self-checking

Single I.S. states-based self-checking

First experimental results Qrs benchmark Target Technology Alcatel CMOS.35 VLSI

Self-checking design theory the fault-secure property the self-testing property the totally self-checking (TSC) property checker structure + system operation modelled faults Φ code inputs A code outputs B

Example Φ={all stuck-at faults} A={01110, 01000, 00111} B={01, 10}

Self-checking design theory Four vectors required to achieve the TSC goal for a parity checker (Khahbaz and McCluskey, TCOMP 1984) 101………….. 011………….. 110………….. 000………….. rows : distinct, same parity each column : exactly 2 1s and 2 0s

Self-exercising parity checker design taken from Tarnick, VLSI Design 1998

1/n checker by Khakbaz, TCOMP 1982 TSC for n>3 generic technology-independent friendly to design automation sometimes criticised as slow, but this does no harm here

Per process 1/n self-checking

Per process 1/n self-checking utilising I.S. states

Experimental results Diffeq benchmark Target Technology Alcatel CMOS.35 VLSI

Conclusion self-checking at the raw, one-hot control signals alternative controller self-checking schemes datapath self-checking resource reuse (Intrinsically Secure States) implementation within a synthesis system, providing full datapath and controller self-checking solutions