George Mason University ECE 545 – Introduction to VHDL ECE 545 Lecture 5 Finite State Machines

2ECE 545 – Introduction to VHDL Arrays

3ECE 545 – Introduction to VHDL Arrays of std_logic_vectors M L(0) L(1) L(2) L(3) L(M-1) L(M) REP_BLOCK

4ECE 545 – Introduction to VHDL Arrays of std_logic_vectors TYPE sig_array IS ARRAY(0 TO M) OF STD_LOGIC_VECTOR(31 DOWNTO 0); … SIGNAL L: sig_array; … BEGIN L(0) <= A; CASCADE: for I in 1 to M generate C: REP_BLOCK port map(REP_IN => L(I-1), REP_OUT=>L(I)); END GENERATE; Z <= L(M); END Structural;

5ECE 545 – Introduction to VHDL Finite State Machine Resources Volnei A. Pedroni, Circuit Design with VHDL Chapter 8, State Machines Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 6, Finite State Machines Chapter 10, Getting the Most from Your State Machine

6ECE 545 – Introduction to VHDL Structure of a Typical Digital System Execution Unit (Datapath) Control Unit (Control) Data Inputs Data Outputs Control Inputs Control Outputs Control Signals

7ECE 545 – Introduction to VHDL Execution Unit (Datapath) Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task Examples of Resources Adders, Multipliers, Registers, Memories, etc.

8ECE 545 – Introduction to VHDL Control Unit (Control) Controls Data Movements in an Operational Circuit by Switching Multiplexers and Enabling or Disabling Resources Follows Some ‘Program’ or Schedule Often Implemented as Finite State Machine or collection of Finite State Machines

9ECE 545 – Introduction to VHDL Finite State Machines Refresher

10ECE 545 – Introduction to VHDL Finite State Machines (FSMs) Any Circuit with Memory Is a Finite State Machine Even computers can be viewed as huge FSMs Design of FSMs Involves Defining states Defining transitions between states Optimization / minimization Above Approach Is Practical for Small FSMs Only

11ECE 545 – Introduction to VHDL Moore FSM Output Is a Function of a Present State Only Present State Register Next State function Output function Inputs Present State Next State Outputs clock reset

12ECE 545 – Introduction to VHDL Mealy FSM Output Is a Function of a Present State and Inputs Next State function Output function Inputs Present State Next State Outputs Present State Register clock reset

13ECE 545 – Introduction to VHDL Moore Machine state 1 / output 1 state 2 / output 2 transition condition 1 transition condition 2

14ECE 545 – Introduction to VHDL Mealy Machine state 1 state 2 transition condition 1 / output 1 transition condition 2 / output 2

15ECE 545 – Introduction to VHDL Moore vs. Mealy FSM (1) Moore and Mealy FSMs Can Be Functionally Equivalent Equivalent Mealy FSM can be derived from Moore FSM and vice versa Mealy FSM Has Richer Description and Usually Requires Smaller Number of States Smaller circuit area

16ECE 545 – Introduction to VHDL Moore vs. Mealy FSM (2) Mealy FSM Computes Outputs as soon as Inputs Change Mealy FSM responds one clock cycle sooner than equivalent Moore FSM Moore FSM Has No Combinational Path Between Inputs and Outputs Moore FSM is more likely to have a shorter critical path

17ECE 545 – Introduction to VHDL Moore FSM - Example 1 Moore FSM that Recognizes Sequence “10” S0 / 0S1 / 0S2 / reset Meaning of states: S0: No elements of the sequence observed S1: “1” observed S2: “10” observed

18ECE 545 – Introduction to VHDL Mealy FSM - Example 1 Mealy FSM that Recognizes Sequence “10” S0S1 0 / 0 1 / 0 0 / 1 reset Meaning of states: S0: No elements of the sequence observed S1: “1” observed

19ECE 545 – Introduction to VHDL Moore & Mealy FSMs – Example 1 clock input Moore Mealy S0 S1 S2 S0 S0 S0 S1 S0 S0 S0

20ECE 545 – Introduction to VHDL Finite State Machines in VHDL

21ECE 545 – Introduction to VHDL FSMs in VHDL Finite State Machines Can Be Easily Described With Processes Synthesis Tools Understand FSM Description If Certain Rules Are Followed State transitions should be described in a process sensitive to clock and asynchronous reset signals only Outputs described as concurrent statements outside the process

22ECE 545 – Introduction to VHDL Moore FSM Present State Register Next State function Output function Inputs Present State Next State Outputs clock reset process(clock, reset) concurrent statements

23ECE 545 – Introduction to VHDL Mealy FSM Next State function Output function Inputs Present State Next State Outputs Present State Register clock reset process(clock, reset) concurrent statements

24ECE 545 – Introduction to VHDL Moore FSM - Example 1 Moore FSM that Recognizes Sequence “10” S0 / 0S1 / 0S2 / reset

25ECE 545 – Introduction to VHDL Moore FSM in VHDL (1) TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state; U_Moore: PROCESS (clock, reset) BEGIN IF(reset = ‘1’) THEN Moore_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF;

26ECE 545 – Introduction to VHDL Moore FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;

27ECE 545 – Introduction to VHDL Mealy FSM - Example 1 Mealy FSM that Recognizes Sequence “10” S0S1 0 / 0 1 / 0 0 / 1 reset

28ECE 545 – Introduction to VHDL Mealy FSM in VHDL (1) TYPE state IS (S0, S1); SIGNAL Mealy_state: state; U_Mealy: PROCESS(clock, reset) BEGIN IF(reset = ‘1’) THEN Mealy_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Mealy_state IS WHEN S0 => IF input = ‘1’ THEN Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;

29ECE 545 – Introduction to VHDL Mealy FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Mealy_state <= S0; ELSE Mealy_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;

30ECE 545 – Introduction to VHDL Moore FSM – Example 2: State diagram Cz1=  resetn Bz0=  Az0=  w0= w1= w1= w0= w0= w1=

31ECE 545 – Introduction to VHDL Present Next state Output state w=0w=1 z AAB0 BAC0 CAC1 Moore FSM – Example 2: State table

32ECE 545 – Introduction to VHDL Moore FSM Present State Register Next State function Output function Input: w Present State: y Next State Output: z clock resetn process(clock, reset) concurrent statements

33ECE 545 – Introduction to VHDL USE ieee.std_logic_1164.all ; ENTITY simple IS PORT (clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN Moore FSM – Example 2: VHDL code (1)

34ECE 545 – Introduction to VHDL CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; Moore FSM – Example 2: VHDL code (2)

35ECE 545 – Introduction to VHDL Moore FSM – Example 2: VHDL code (3) END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ;

36ECE 545 – Introduction to VHDL Moore FSM Present State Register Next State function Output function Input: w Present State: y_present Next State: y_next Output: z clock resetn process (w, y_present) concurrent statements process (clock, resetn)

37ECE 545 – Introduction to VHDL ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; Alternative VHDL code (1)

38ECE 545 – Introduction to VHDL WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (clock, resetn) BEGIN IF resetn = '0' THEN y_present <= A ; ELSIF (clock'EVENT AND clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ; Alternative VHDL code (2)

39ECE 545 – Introduction to VHDL A w0=z0=  w1=z1=  B w0=z0=  resetn w1=z0=  Mealy FSM – Example 2: State diagram

40ECE 545 – Introduction to VHDL Present Next stateOutput z state w=0w=1w=0w=1 AAB00 BAB01 Mealy FSM – Example 2: State table

41ECE 545 – Introduction to VHDL Mealy FSM Next State function Output function Input: w Present State: y Next State Output: z Present State Register clock resetn process(clock, reset) concurrent statements

42ECE 545 – Introduction to VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Mealy IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END Mealy ; ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN Mealy FSM – Example 2: VHDL code (1)

43ECE 545 – Introduction to VHDL Mealy FSM – Example 2: VHDL code (2) CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ;

44ECE 545 – Introduction to VHDL Mealy FSM – Example 2: VHDL code (3) END IF ; END PROCESS ; WITH y SELECT z <= w WHEN B, z <= ‘0’ WHEN others; END Behavior ;

45ECE 545 – Introduction to VHDL State Encoding

46ECE 545 – Introduction to VHDL State Encoding Problem State Encoding Can Have a Big Influence on Optimality of the FSM Implementation No methods other than checking all possible encodings are known to produce optimal circuit Feasible for small circuits only Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool

47ECE 545 – Introduction to VHDL Types of State Encodings (1) Binary (Sequential) – States Encoded as Consecutive Binary Numbers Small number of used flip-flops Potentially complex transition functions leading to slow implementations One-Hot – Only One Bit Is Active Number of used flip-flops as big as number of states Simple and fast transition functions Preferable coding technique in FPGAs

48ECE 545 – Introduction to VHDL Types of State Encodings (2) StateBinary CodeOne-Hot Code S S S S S S S S

49ECE 545 – Introduction to VHDL (ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; ATTRIBUTE ENUM_ENCODING : STRING ; ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS " " ; SIGNAL y_present, y_next : State_type ; BEGIN con’t... Figure 8.34 A user-defined attribute for manual state assignment

50ECE 545 – Introduction to VHDL Using constants for manual state assignment (1) ARCHITECTURE Behavior OF simple IS SUBTYPE ABC_STATE is STD_LOGIC_VECTOR(1 DOWNTO 0); CONSTANT A : ABC_STATE := "00" ; CONSTANT B : ABC_STATE := "01" ; CONSTANT C : ABC_STATE := "11" ; SIGNAL y_present, y_next : ABC_STATE; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; … con’t