정 용 군 ( 전자공학과 대학원 ) 대상 : VLSI 설계 연구회 1,2,3 학년 기간 : ~ Synopsys Tool 교육 Synopsys 교육 1

Design Analyzer HDL Compiler Family HDL Synthesis HDL Compiler TM VHDL Compiler TM (verilog) Design Compiler Family Circuit optimization Design Compiler TM FPGA Compiler TM (CMOS) Test Compiler Family Test Compiler TM Test Compiler Plus TM VHDL System Simulation SGE VHDL Netlist Schematics State tables Test Vector Technology Library Compiler Netlist Schematics State tables Goals Verilog DesignWare Develop Synopsys 의 구조

Synopsys 교육 1 Synopsys 환경 설정 - 자신의.cshrc 파일에 다음을 추가한다.(donald 기준 ) ################# setup for synopsys #################### setenv SYNOPSYS /tools/synopsys set path = ( $path $SYNOPSYS/sparcOS5/syn/bin ) set path = ( $path $SYNOPSYS/sparcOS5/sim/bin ) set path = ( $path $SYNOPSYS/sparcOS5/sge/bin ) set path = ( $path $SYNOPSYS/iview2/bin ) set path = ( $path /opt/SUNWspro/bin ) source $SYNOPSYS/admin/install/sim/environ.csh ######################################################

Synopsys 교육 1 VHDL System Simulator Synthesis with VHDL sge : Simulation Graphical Environment vhdlan : VHDL analyzer gvan : Graphical VHDL analyzer vhdlsim : VHDL simulator vhdldbx : VHDL debugger => Design Analyzer

Synopsys 교육 1 VHDL System Simulator 1. SGE 시작 Ex : [donald:home/grad/dragon]sge &

Synopsys 교육 1 2. Drawing circuits (Schematic editor)

Synopsys 교육 Drawing circuits (Schematic editor) (cont.) : Add / Symbol command Select components to place

Synopsys 교육 Drawing circuits (Schematic editor) (cont.) : Add / Wire command Draw the line to input/ output port of symbols

Synopsys 교육 Drawing circuits (Schematic editor) (cont.) : Add / Netname command => determine netname enter net name * If net is BUS, enter the net name ; A(3:0), B(4:0) etc.

Synopsys 교육 Drawing circuits (Schematic editor) (cont.) : Add / I/O Marker command => determine input/output

Synopsys 교육 Drawing circuits (Schematic editor) (cont.) : File / Save command =>.sch,._sc

Synopsys 교육 1 3. Compile circuits (Schematic editor) : Netlist => VHDL code 3.1. Creating a symbol If select this block, display information of designed circuits automatically generated by Schematic editor

Synopsys 교육 Creating a symbol (cont.) => To simulate and synthesis after transforming netlist to VHDL code => To edit symbol by designer => Must create a symbol for each schematic :.sym

Synopsys 교육 Creating a symbol (cont.) Draw / Rect => draw box

Synopsys 교육 Creating a symbol (cont.) Draw / Line => draw line Add / Pin => determine in/out port

Synopsys 교육 Creating a symbol (cont.) Add / Pin Attr => determine pin name and polarity BUS => A(3:0), B(5:0) pin name change polarity

Synopsys 교육 Creating a symbol (cont.) determine position of pin name Add / Pin Name Loc

Synopsys 교육 Creating a symbol (cont.) Add / Window Using the symbol created, is placed with this shape

Synopsys 교육 Creating a symbol (cont.)

Synopsys 교육 Generate VHDL code vi editor Netlist => VHDL code

Synopsys 교육 1 4. Simulation => It is the most useful method using test bench. 4.1 Test Bench Generation 1) automatic generation by SGE 2) code test bench for yourself

Synopsys 교육 Automatic generation by SGE

Synopsys 교육 Automatic generation by SGE (cont.) : Tools / Code VHDL Models => tb_(circuit-name).vhd generate test bench Test bench is automatically generated, but insert input signal to test bench with using editor program(vi)

Synopsys 교육 Automatic generation by SGE (cont.) : Tools / Analyze VHDL Models => compile test bench

Synopsys 교육 Automatic generation by SGE (cont.) : Tools / Start VHDL Simulator => compile test bench VHDL debugger (vhdldbx) WAVE

Synopsys 교육 Coding test bench for yourself Designed circuit test bench input signal output signal structual description

Synopsys 교육 1 Example of input signals for test bench clock of 250 ns period reset signal

Synopsys 교육 Simulation vhdlan vhdldbxwave vhdl source test bench error OK

Synopsys 교육 vhdlan (shell mode) usage : vhdlan [option] (vhdl source, test bench) [option] -l : read vhdl file and generate *.lis file having error message -c : generate object code compiled -v : display information of analyzer Ex : vhdlan -l -c test.vhd cf) graphic mode : gvan

Synopsys 교육 vhdldbx ( ex : [donald:home/grad/dragon/WORK]vhdldbx & ) select configuration 1. include *.log 2. run edit *.log file : have information in/out port being displayed in wave window ex) vi test.log trace clk trace a[0].

Synopsys 교육 wave ( ex : [donald:home/grad/dragon/WORK]waves & ) waveform file *.ow

Synopsys 교육 wave ( ex : [donald:home/grad/dragon/WORK]waves & ) (cont.)

Synopsys 교육 1 Synthesis with VHDL Design Compiler Design Operating Environment Description Timing, Area and Design Rule Goals Optimized design Reports Schematics Inputs and Outputs of Design Compiler `

Synopsys 교육 1 Menu command line Design Compiler design_analyzer (graphical mode) dc_shell (shell mode) Design Compiler Interaction

Synopsys 교육 1 Design analyzer 실행 Ex : [donald:home/grad/dragon]design_analyzer &

Synopsys 교육 1 File / Read command => To read designs into Design Compiler Read formats; DB EDIF Equation LSI Mentor PLA State table Tegas Verilog VHDL

Synopsys 교육 1 File / Analyze command => syntax checks VHDL code,.syn and.mra file 생성 vhdl source file find file to analyze Library is the name of working directory. determine format to analyze

Synopsys 교육 1 File / Elaborate command => elaborate after analyze to bring design into Design Compiler memory select working directory name automatically re-analyzes out of date intermediate files if source can be found * If you change VHDL code, analyze and elaborate again

Synopsys 교육 1 Analysis / Link Design command => To ensure all sub-elements of your hierarchical designs are available.

Synopsys 교육 1 Analysis / Check Design command => execute check design before you optimize your design

Synopsys 교육 1 Attributes / Clock command

Synopsys 교육 1 Design Optimization 1. Constraints

Synopsys 교육 1 2. Design optimization => type of CLB and IOB of Xilinx

Synopsys 교육 1 FPGA