Chapter 2 Summary Classification of architectures Features that are relatively independent of instruction sets “Different” Processors –DSP and media processors Impact of compilers

Appendix A, Chapters Three and Four Pipelining

Introduction “Assembly line” execution Multiple pipe stages (or pipe segments) Ideally: Or:

Introduction (cont.) There are overheads due to the pipeline Three views: –Reducing CPI –Reducing clock cycle time –A combination Major advantage: Invisible to programmers

Implementation of MIPS Without pipelining: –Five clock cycles: Instruction fetch (IF) Instruction decode/register fetch/branch resolution (ID) Execution/Effective address calc. (EX) Memory access (MEM) Write-back (WB) –Branch requires two cycles, store requires four cycles –CPI: 4.54

The Basic Pipeline for MIPS Each cycle becomes a pipe stage Need to ensure hardware is not used in more than one stage –E.g. ALU for PC incrementing –Register accesses Can use half cycles –Memory accesses Can use separate caches

Basic Pipeline Branches become problematic –IF is first stage –Branch resolved in ID (2 nd ) stage Registers required between stages –Pipeline registers (or pipeline latches) –Carry data and control signals

Performance Pipeline runs at speed of slowest stage Overheads due to: –Pipeline registers –Clock skew

A.2. Pipeline Hazards Prevent execution of next instruction Three classes: –Structural hazards Hardware contention –Data hazards Data dependencies –Control hazards PC-changing instructions

Pipeline Hazards May need to stall the pipeline Performance impact (simplified):

Structural Hazards Resource contention E.g. one memory port –IF stalls when there is a data-memory access Introduces a pipeline bubble

Why Allow Structural Hazards? Expense Reduced latency –Simple, non-pipelined unit may run faster –E.g. FP units

Data Hazards Dependent instructions add %g1, %g2, %g3 sub %l1, %g3, %o0 Result available in WB, needed in ID Non-deterministic!

Data Hazards Problem may span several cycles add %l0, %i0, %g3 sub %l1, %g3, %o0 ! Problem and %l2, %g3, %o1 ! Problem or %l3, %g3, %o2 xor %l4, %g3, %o3 ! OK

Minimising Impact of Data Hazards Simple hardware technique: forwarding (or bypassing, or short-circuiting) Feed ALU output back as an ALU input –Hardware detects hazard –Ignores fetched register value –Selects forwarded result

Forwarding Need to include all functional units add %g1, %g2, %g3 sw %g3, [%fp-12]

Data Hazards Requiring Stalls Cannot prevent all stalls lw [%fp-12], %g3 add %g3, %l0, %l1 A pipeline interlock detects the hazard and stalls the pipeline MIPS: 1 clock cycle

What is the impact? Assume 30% of instructions are loads; 50% of these are followed by a dependent instruction; the ideal CPI is 1.