Catapult™ C Synthesis Crossing the Gap between Algorithm and Hardware Architecture Mac Moore North American Product Specialist Advanced Synthesis Solutions MAPLD 2005

Introducing Catapult C Synthesis n Catapult C Synthesis launched May 31 st, 2004 — 100+ man years of research and development — 3 years of customer proof and validation — Initial focus on wireless companies: STMicroelectronics, Nokia, Ericsson n Product took center stage at DAC 2004 — “ Most important announcement at DAC” - Gary Smith, Dataquest — No. 1 “must see” product - Gartner Dataquest annual DAC list n Catapult news in 2005 — EDN Top 100 products — John Cooley’s DAC must see list — Recent Press Releases: SystemC verification extension, Fraunhofer, Panasonic, Sanyo customer adoption Front Page -EETimes

Catapult C Synthesis – Algorithm to RTL Develop Algorithms using ANSI C++ No proprietary extension Focus on the functional intent Develop Algorithms using ANSI C++ No proprietary extension Focus on the functional intent Synthesize with Catapult C Explore the design space Find the optimal architecture Synthesize with Catapult C Explore the design space Find the optimal architecture Technology Files Technology Files Architectural Constraints Architectural Constraints Generate High Speed Models Verilog, VHDL, SystemC Accelerate system level verification Generate High Speed Models Verilog, VHDL, SystemC Accelerate system level verification Untimed TLM Timed TLM Cycle TLM Generate Target Optimized RTL Faster and better than hand-coded For ASIC, FPGA or FPGA prototyping of ASICs Generate Target Optimized RTL Faster and better than hand-coded For ASIC, FPGA or FPGA prototyping of ASICs Automatically Verify the RTL Generation of testbench infrastructure Seamlessly reuse original C++ test vectors Automatically Verify the RTL Generation of testbench infrastructure Seamlessly reuse original C++ test vectors

Optimized Design Architecture n Exhaustive design space exploration n Often yields superior designs over hand-coded RTL Algorithmic C++ RTL Optimization Scope Local Minima X X Architectural Scenarios Area Global Minima – Out of Reach Within Reach! X IP Block A A A A A Result

Incremental Design Analysis n Analysis tools tackle algorithm complexity and interactively converge to the optimal solution n “Cause-and-Effect” cross-probing links any result with the original C source n Graphical reports provide better understanding of synthesis results n Ease-of-Use smooths learning curve and facilitates tool adoption n User interface built on live database — Incremental analysis — Incremental exploration — Incremental optimization

Customer Adoption n Design types — Filters (FIR, IIR…) — Tranforms (FFT, DCT …) — Equalizers — Interleavers — FEC (Viterbi, Reed Solomon…) — Video Line Filters — JPEG/MPEG Pixel pipes — … n Applications: — Wireless Communications — Satellite Communications — WLAN — Base Stations — VoIP — Sound Broadcast — Video and Multimedia — Digital TV — Storage — Aerospace & Military — …

Catapult C Synthesis Summary n Only pure ANSI C++ algorithmic synthesis tool — Easiest to write, most concise, fastest to simulate, best results n 1st production quality C++ tool — Over 30 completed ASIC & FPGA designs — Documented case studies, references and testimonials n Used by top customers worldwide — ST, Ericsson, Nokia, Alcatel, Siemens, Panasonic, Sanyo n Focus: Engineers developing complex wireless and video hardware — Yields safer silicon with fewer bugs — More efficient design flow yielding smaller hardware in less time — Automated verification flow