Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 9 IC Fabrication Process Overview

Major Fabrication Steps in MOS Process Flow Used with permission from Advanced Micro Devices Oxidation (Field oxide) Silicon substrate Silicon dioxide oxygen Photoresist Develop oxide Coating photoresist Mask-Wafer Alignment and Exposure Mask UV light Exposed exposed G S D Active Regions top nitride silicon nitride Nitride Deposition Contact holes Etch Ion Implantation resist ox Scanning ion beam Metal Deposition and Etch drain Metal contacts Polysilicon polysilicon Silane gas Dopant gas (Gate oxide) gate oxide Strip RF Power Ionized oxygen gas Oxide Ionized CF4 gas Mask and Etch Ionized CCl4 gas poly gate Used with permission from Advanced Micro Devices Figure 9.1

Overview of Areas in a Wafer Fab CMOS Process Flow Overview of Areas in a Wafer Fab Diffusion Photolithography Etch Ion Implant Thin Films Polish CMOS Manufacturing Steps Parametric Testing

Model of Typical Wafer Flow in a Sub-Micron CMOS IC Fab Test/Sort Implant Diffusion Etch Polish Photo Completed Wafer Unpatterned Wafer Wafer Start Thin Films Wafer Fabrication (front-end) Used with permission from Advanced Micro Devices Figure 9.2

CMOS Manufacturing Steps Passivation layer Bonding pad metal p+ Silicon substrate LI oxide STI n-well p-well ILD-1 ILD-2 ILD-3 ILD-4 ILD-5 M-1 M-2 M-3 M-4 Poly gate p- Epitaxial layer p+ ILD-6 LI metal Via n+ 2 3 1 4 5 6 7 8 9 10 11 12 13 14 1. Twin-well Implants 2. Shallow Trench Isolation 3. Gate Structure 4. Lightly Doped Drain Implants 5. Sidewall Spacer 6. Source/Drain Implants 7. Contact Formation 8. Local Interconnect 9. Interlayer Dielectric to Via-1 10. First Metal Layer 11. Second ILD to Via-2 12. Second Metal Layer to Via-3 13. Metal-3 to Pad Etch 14. Parametric Testing

n-well Formation Figure 9.8

p-well Formation Figure 9.9

STI Trench Etch Figure 9.10

STI Oxide Fill Figure 9.11

STI Formation Figure 9.12

Poly Gate Structure Process Figure 9.13

n- LDD Implant Figure 9.14

p- LDD Implant Figure 9.15

Side Wall Spacer Formation Figure 9.16

n+ Source/Drain Implant Figure 9.17

p+ Source/Drain Implant Figure 9.18

Contact Formation Figure 9.19

LI Oxide as a Dielectric for Inlaid LI Metal (Damascene) Figure 9.20

LI Oxide Dielectric Formation Figure 9.21

LI Metal Formation Figure 9.22

Via-1 Formation Figure 9.23

Plug-1 Formation Figure 9.24

SEM Micrographs of Polysilicon, Tungsten LI and Tungsten Plugs Micrograph courtesy of Integrated Circuit Engineering Polysilicon Tungsten LI Tungsten plug Mag. 17,000 X Photo 9.4

Metal-1 Interconnect Formation Figure 9.25

SEM Micrographs of First Metal Layer over First Set of Tungsten Vias Micrograph courtesy of Integrated Circuit Engineering TiN metal cap Mag. 17,000 X Tungsten plug Metal 1, Al Photo 9.5

Via-2 Formation Figure 9.26

Plug-2 Formation Figure 9.27

Metal-2 Interconnect Formation Figure 9.28

Full 0.18 mm CMOS Cross Section Passivation layer Bonding pad metal p+ Silicon substrate LI oxide STI n-well p-well ILD-1 ILD-2 ILD-3 ILD-4 ILD-5 M-1 M-2 M-3 M-4 Poly gate p- Epitaxial layer p+ n+ ILD-6 LI metal Via Figure 9.29

SEM Micrograph of Cross-section of AMD Microprocessor Micrograph courtesy of Integrated Circuit Engineering Mag. 18,250 X Photo 9.6

Photo courtesy of Advanced Micro Devices Wafer Electrical Test using a Micromanipulator Prober (Parametric Testing) Photo courtesy of Advanced Micro Devices Photo 9.7