Shantanu Dutt ECE Dept. UIC ECE 565: VLSI Design Automation Introduction: VLSI Design Flow & Logic Opt./Tech. Mapping Shantanu Dutt ECE Dept. UIC Acknowledegements: Some slides are from publicly available slides by Naveed Sherwani (VLSI design flow) and S. Devadas (logic opt.)

Opt. metrics: -- Speed -- Power -- WL/area Other metrics (constraints): -- Temperature -- temperature

IC Design Steps (cont.) High-level Description Functional Description Specifications Behavioral VHDL, C Structural VHDL These steps are not etched in stone: there are lots of varieties High-level description defines major components of the design and their interaction Functional description is usually at Register Transfer Level (RTL). RTL description deals with more details, lists signals, block components. Languages such as VHDL are used to describe the architecture. Figs. [©Sherwani]

IC Design Steps (cont.) Synthesis Physical Design Technology Mapping High-level Description Functional Description Specifications Synthesis HLS Physical Design Technology Mapping Placed & Routed Design Logic Description Gate-level Design Again, these steps are not etched in stone: there are lots of varieties Logic description is usually generated by Computer Aided Design (CAD) tools Gate-level design (also known as “netlist”) describes the design in the atomic entities of the technology. For a CMOS design, transistors are used. In an FPGA design, look-up tables (LUTs) are used. The process of converting a logic description to a gate-level design is called technology mapping. There are a *lot* of optimizations involved after technology mapping We might go back and forth between these steps (e.g., after gate-level desc., we might simulate and find bugs => go back to RTL or high-level description and fix the bug) I haven’t shown testing/verification This course helps you understand the methods and algorithms used for automatic high-level synthesis and and physical design You will develop small CAD tools that do these steps automatically. Fabri- cation X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Packaging Figs. [©Sherwani]

RTL Design Flow Library/ module generators HDL RTL manual Synthesis Includes HLS Library/ module generators HDL RTL Synthesis manual design netlist a b s q 1 d clk logic optimization Logic opt. + Technology mapping netlist a b s q 1 d clk Circuit resynthesis (e.g., buff. Ins., cell replication) physical design layout

Logic optimization flow LOGIC EQUATIONS Factoring Commonality Extraction TECHNOLOGY-INDEPENDENT OPTIMIZATION TECH-DEPENDENT OPTIMIZATION (TECH. MAPPING, TIMING) LIBRARY OPTIMIZED LOGIC NETWORK

Logic optimization flow LOGIC EQUATIONS Factoring Commonality Extraction TECHNOLOGY-INDEPENDENT OPTIMIZATION TECH-DEPENDENT OPTIMIZATION (TECH. MAPPING, TIMING) LIBRARY OPTIMIZED LOGIC NETWORK

Why logic optimization? Transistor count redution AREA Circuit count redution POWER Gate count (fanout) reduction DELAY (Speed) Area reduction, power reduction and delay reduction improves design

Boolean Optimizations Involves: Finding common subexpressions. Substituting one expression into another. Factoring single functions. Find common expressions Extract and substitute common expression f1 = AB + AC + AD + AE + A B C D E ì F = í î f2 = A B + A C + A D + A F + A B C D F f1 = A ( B + C + D + E ) + A B C D E ì F = í î f2 = A ( B + C + D + F ) + A B C D F g1 = B + C + D ì G = í f1 = A ( g1 + E ) + A E g1 ï î f2 = A ( g1 + F ) + A F g1

Algebraic Optimizations Algebraic techniques view equations as polynomials Rules of polynomial algebra are used For e.g. in algebraic substitution (or division) if a function f = f(a, b, c) is divided by g = g(a, b), a and b will not appear in f / g Boolean algebra rules are not applied

Logic optimization flow LOGIC EQUATIONS Factoring Commonality Extraction TECHNOLOGY-INDEPENDENT OPTIMIZATION TECH-DEPENDENT OPTIMIZATION (TECH MAPPING, TIMING) LIBRARY OPTIMIZED LOGIC NETWORK

Standard cell library For each cell (e.g., NANDs, NORs, Invs, AOIs) Functional information Timing information Input slew Intrinsic delay Output capacitance Physical footprint Power characteristics

Sample Library INVERTER 2 NAND2 3 NAND3 4 NAND4 5

Sample Library - 2 AOI21 4 AOI22 5

Mapping via DAG* Covering Represent network in canonical form Þ subject DAG Represent each library gate with canonical forms for the logic function Þ primitive DAGs Each primitive DAG has a cost Goal: Find a minimum cost covering of the subject DAG by the primitive DAGs * Directed Acyclic Graph

Trivial Covering Reduce netlist into ND2 gates → subject DAG 7 NAND2 = 21 5 INV = 10 31 (area cost)

Covering #1 2 INV = 4 2 NAND2 = 6 1 NAND3 = 4 1 NAND4 = 5 19 (area cost)

Covering #2 1 INV = 2 1 NAND2 = 3 2 NAND3 = 8 1 AOI21 = 4 17 (area cost)

Multiple fan-out

Partitioning a Graph Partition input netlist into a forest of trees Solve each tree optimally Stitch trees back together

Optimum Tree Covering INV 11 + 2 = 13 AOI21 4 + 3 = 7 NAND2 2 + 6 + 3 = 11 NAND2 3 + 3 = 6 INV 2 NAND2 3 NAND2 3

DAG Covering steps Partition DAG into a forest of trees Normalize the netlist Optimally cover each tree Generate all candidate matches Find optimal match using dynamic programming

For more details on logic opt. … Refer to Srinivas Devadas’ slides for 6.373 http://csg.csail.mit.edu/u/d/devadas/public_html/6.373/lectures/