ECE 8053 – Project Fall’02 Design of 64-bit Low Power Spanning Tree Carry Lookahead Adder Presented by Suderson Soundararajan.

Slides:

Advertisements

Similar presentations

EVALUATION OF A CIRCUIT PATH DELAY TUNING TECHNIQUE FOR NANOMETER CMOS Advisor: Dr. Adit D. Singh Committee members: Dr. Vishwani D. Agrawal and Dr. Victor.

Advertisements

VLSI Arithmetic Adders & Multipliers

1 Specifications Functionality: AND, OR, XOR, ADD Maximum propagation delay : 2ns Power budget: 30mW Area: 200 µm ×400µm Prepared by: Christie Ma, Manjul.

Introduction So far, we have studied the basic skills of designing combinational and sequential logic using schematic and Verilog-HDL Now, we are going.

CPE 626 CPU Resources: Adders & Multipliers Aleksandar Milenkovic Web:

EE141 © Digital Integrated Circuits 2nd Arithmetic Circuits 1 Digital Integrated Circuits A Design Perspective Arithmetic Circuits Jan M. Rabaey Anantha.

EE141 Adder Circuits S. Sundar Kumar Iyer.

SYEN 3330 Digital SystemsJung H. Kim Chapter5-1 1 SYEN 3330 Digital Systems Chapter 5 – Part 1.

Ch.3 Overview of Standard Cell Design

Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a1 Design for Testability Theory and Practice Lecture 4a: Simulation n What is simulation? n Design.

Redesign control FSM of a multicycle MIPS processor with low power state encoding.

San Jose State University Department of Electrical Engineering Dec 5th, Fall 2005 EE 166 PROJECT Advisor: Prof. David Parent Group Members Radhika Arora,

1 4-BIT ARITHMETIC LOGIC UNIT Motorola MC54/74F181 Heungyoun Kim Lu Gao Jun Li Advisor: Dr. David W. Parent DATE: 12/05/2005.

Nov. 29, 2005 ELEC Class Presentation 1 Logic Redesign for Low Power ELEC 6970 Project Presentation By Nitin Yogi.

VLSI Arithmetic Adders Prof. Vojin G. Oklobdzija University of California

1 Design of 8- Bit ALU Neelam Chaudhari Archana Mulukutla Namita Mittal Madhumita Sanyal Advisor : Dr. David Parent Date : May 8, 2006.

1 DESIGN OF 4-BIT ALU Fairchild Semiconductor DM74LS181 Prashanth Kommuri Akram Khan Gopinath Akkinepally Advisor: Dr. David W. Parent 5 December 2005.

1 4 Bit ALU with Carry Look Ahead Generator Piyu Singh Dhaker Kedar Bhatawadekar Nikhat Baig Advisor: Dave Parent DATE:12/05/05.

1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 5 MAD MAC nd February, 2006 Top Level Integration.

1 Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.

ECE x26 Laboratory 4 Pavan Gunda. Overview Lab4 is the culmination of all your efforts of both the ECE x25 and ECE x26 labs. Integrates the designs built.

SADDAPALLI RUDRA ABHISHEK

1 4-Bit ALU Chun-Wai Lee Shiela Valenciano Advisor: Dr. David Parent 12/05/05.

Low Power RF/Analog Amplifier Design Tong Zhang Auburn University Tong Zhang Auburn University.

CSE241 RTL Performance.1Kahng & Cichy, UCSD ©2003 CSE241A VLSI Digital Circuits Winter 2003 Recitation 2.5: Performance Coding.

1 DESIGN OF 8-BIT ALU Vijigish Lella Harish Gogineni Bangar Raju Singaraju Advisor: Dr. David W. Parent 8 May 2006.

Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Arithmetic Building Blocks.

4 Bit ALU Geeping (Frank) Liu, Kasem Tantanasiriwong,

1 8 Bit ALU EE 166 Design Project San Jose State University Roger Flores Brian Silva Chris Tran Harizo Yawary Advisor: Dr. Parent May 2006.

8-Bit Gray Code Converter

Digital System Design Verilog ® HDL Maziar Goudarzi.

Spring 2002EECS150 - Lec10-cl1 Page 1 EECS150 - Digital Design Lecture 10 - Combinational Logic Circuits Part 1 Feburary 26, 2002 John Wawrzynek.

An Extra-Regular, Compact, Low-Power Multiplier Design Using Triple-Expansion Schemes and Borrow Parallel Counter Circuits Rong Lin Ronald B. Alonzo SUNY.

Mixed Logic Circuit Design

Adders. Full-Adder The Binary Adder Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB.

Lec 17 : ADDERS ece407/507.

Parallel Prefix Adders A Case Study

32-BIT ADDER FOR LOW VOLTAGE OPERATION WITH LEVEL CONVERTERS PRIYADHARSHINI S.

Abdullah Aldahami ( ) Feb26, Introduction 2. Feedback Switch Logic 3. Arithmetic Logic Unit Architecture a.Ripple-Carry Adder b.Kogge-Stone.

Arithmetic Building Blocks

DCSL & LVDCSL: A High Fan-in, High Performance Differential Current Switch Logic Families Dinesh Somasekhaar, Kaushik Roy Presented by Hazem Awad.

CSE 494: Electronic Design Automation Lecture 2 VLSI Design, Physical Design Automation, Design Styles.

A 240ps 64b Carry-Lookahead Adder in 90nm CMOS Faezeh Montazeri Advanced VLSI Course Presentation University of Tehran December.

Low Power – High Speed MCML Circuits (II)

Design of a 32-Bit Hybrid Prefix-Carry Look-Ahead Adder

Low-Power and Area-Efficient Carry Select Adder on Reconfigurable Hardware Presented by V.Santhosh kumar, B.Tech,ECE,4 th Year, GITAM University Under.

MOTION ESTIMATION IMPLEMENTATION IN VERILOG

L 19: Low Power Circuit Optimization. Power Optimization Modeling and Technology Circuit Design Level –logic Families –low-power Flip-Flops –low-power.

A Reconfigurable Low-power High-Performance Matrix Multiplier Architecture With Borrow Parallel Counters Counters : Rong Lin SUNY at Geneseo

Design of an 8-bit Carry-Skip Adder Using Reversible Gates Vinothini Velusamy, Advisor: Prof. Xingguo Xiong Department of Electrical Engineering, University.

L12 – VHDL Overview. VHDL Overview  HDL history and background  HDL CAD systems  HDL view of design  Low level HDL examples  Ref: text Unit 10, 17,

Spring C:160/55:132 Page 1 Lecture 19 - Computer Arithmetic March 30, 2004 Sukumar Ghosh.

1 A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, and Tsai-Wen.

Project submitted By RAMANA K VINJAMURI VLSI DESIGN ECE 8460 Spring 2003.

UC Berkeley, Dept of EECS EE141, Fall 2005, Project 2 Speed/Area Optimized 8-bit Adder Design Name 1 Name 2 Delay(  s) ·Area(  m 2 ) = {your number}

Integrated VLSI Systems EEN4196 Title: 4-bit Parallel Full Adder.

IMPLEMENTATION OF MIPS 64 WITH VERILOG HARDWARE DESIGN LANGUAGE BY PRAMOD MENON CET520 S’03.

LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGA Project Guide: Smt. Latha Dept of E & C JSSATE, Bangalore. From: N GURURAJ M-Tech,

Unrolling Carry Recurrence

Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Arithmetic Building Blocks.

Computer Architecture Mid-term review Ralph Grishman Oct NYU.

64 bit Kogge-Stone Adders in different logic styles – A study Rob McNish Satyanand Nalam.

A Method for Reducing Active and Leakage Power in Kogge-Stone Adder VLSI Design – ECE6332 Elaheh Sadredini Luonan Wang December 02, 2014.

C OMBINATIONAL L OGIC D ESIGN 1 Eng.Maha AlGubali.

EE141 Arithmetic Circuits 1 Chapter 14 Arithmetic Circuits Rev /12/2003.

1 Architecture of Datapath- oriented Coarse-grain Logic and Routing for FPGAs Andy Ye, Jonathan Rose, David Lewis Department of Electrical and Computer.

Area- and Power-Reduced Standard-Cell Spanning Tree Adders

VLSI Arithmetic Lecture 4

Measuring the Gap between FPGAs and ASICs

Presentation transcript:

ECE 8053 – Project Fall’02 Design of 64-bit Low Power Spanning Tree Carry Lookahead Adder Presented by Suderson Soundararajan

Overview Introduction Design Optimization for Power Optimization for Performance Optimization for Area Usage of CAD tools Presentation of Results and Comparison Summary and Conclusion References

Design

Optimization for Power Low Power and High Performance Full Adder Cell Full Adder Cell – A Novel High Performance CMOS 1-bit Full Adder cell, Ahmed M.Shams, Bayoumi, M.A

Optimization for Speed Domino! Two-Phase Clock – Generated using Chopper Circuit

Optimization for Speed Contd.. MCC – Group Propagate Signal Generation MCC – Group Generate Signal Generation

Optimization for Area 4-bit Carry Select Adder - Youngjoon Kim; Lee-Sup Kim. “A Low Power Carry Select adder with Reduced Area” Less Number of Transistors => Less Area

Delay and Power Dissipation MCC Blocks MCC3MCC2 Delay 420 ps300 ps Power 15 uW11 uW

Usage of CAD tools Functionality Verification - Gate Level Verilog – ModelSim Synthesis - Flattened Netlist – Synopsys Transistor Level Simulation and Testing - Netlist - Cadence Spectre

Delay2.4 ns3.2 ns Power5.7 mW3.6 mW Results Comparison ParametersDelayTransistor Count Spanning Tree Carry Lookahead Adder 3.2 ns6390 Variable Spanning Tree Carry Lookahead Adder 2.8 ns5671 Hybrid Spanning Tree Carry Lookahead Adder 2.4 ns2475

Conclusion Achieved Low Power and High Performance compared to the conventional one Can still optimize for Power – Carry Lookahead Scheme Can still optimize for Speed – Sizing!

References Thomas Lynch, Earl E.Swartzlander, “A Spanning Tree Carry Lookahead Adder,” IEEE transactions, Vol 41, No.8, August Jeffrey Blackburn, Lisa Amdt, Earl E.Swartzlander, “Optimization of Carry Lookahead Adders”, 1997, IEEE transactions. Ahmed M.Shams, Bayoumi, M.A, “A Novel High Performance CMOS 1-bit Full Adder Cell”, IEEE transactions, Vol.47, No.5, May’2000. Youngjoon Kim; Lee-Sup Kim. “A Low Power Carry Select adder with Reduced Area, Circuits and Systems,” ISCAS The 2001 IEEE International Symposium on, Volume: 4, 2001 Page(s): 218 – 221