Electronic Engineering Final Year Project 2008 By Claire Mc Kenna Title: Point of Load (POL) Power Supply Design Supervisor: Dr Maeve Duffy

Project Outline Objective is to compare the industry used Dc-Dc Voltage Regulator Module (VRM) the (Interleaved Buck Converter) with a conventional power converter. Conventional power converter V.I Chips, PRM and VTM made by Vicor Corporation. Pre-Regulator Module (PRM) and Voltage Transformation Module (VTM) chips.

Background Operating voltages for microprocessors are getting smaller e.g. 1V. At present the Intel Xeon (LV) processor operates at 1.1V. As the operating voltage is reduced the current drawn is increased. Higher current results in higher dissipated losses in mosfets and copper paths.

Background As switching frequency increases, the switching losses increase. Vicor have proposed a high current low voltage solution providing low voltage high current (100A) direct from 48V input. Compare the V.I chips and the alternative solution under steady state and transient load conditions.

Progress to Date Review of VRM issues for future microprocessor requirements. Research on the PRM and VTM V.I chips Intel launch new 45nm microarchitecture with energy efficiency technology, so far no information on power requirements or VRM design. Review of Buck converter using Pspice. Review of the Multiphase Interleaved Buck Converter.

Progress to Date Review of the Buck Converter Using the parameters below Pspice was used to simulate the transient and steady state of the buck converter. Vin = 12V Vo = 1.3V F = 500Khz Io = 100A The duty cycle was found to be and the period 2us. L = 23.18nH and C = uF

Progress to Date Vout was less than 1.3V due to the switching losses and voltage drops from the mosfet and diodes. By varying the duty to 1.9us the highest it would go 1V was obtained at the output. The output current was reduced to 10A and new inductor and capacitor values were calculated.

Progress to Date Varying the duty to the output voltage of 1.3V was obtained. Current ripple was calculated to be 9.97A and the measured value obtained was 9.996A.

Progress to Date Two phases of the interleaved buck was simulated. By driving the mosfets 1us apart introduces the interleaving effect which is the ripple cancellation in the output capacitor. The duty was adjusted and the correct output voltage and current was obtained. Transient load change was also simulated.

Project Plan Order the VI chips so testing can begin and to compare with simulated results. Review the circuit diagrams of VTM and PRM and simulate in Pspice. Magnetic component design of a suitable inductor/transformer for both VI chips and Buck Converter. Build and test for both solutions.

Proposals (Time Scale) Now – Review of the PRM/VTM chips. Feb - Magnetic component design for V.I chips and Buck converter. Late Feb/Early March – Build and test magnetic components for both solutions. March – Consider the implications of future microprocessor requirements for magnetic components.