2008 BBN Quantum Computing Kickoff Quantum Materials David P. Pappas Jeffrey S. Kline, Minhyea Lee National Institute of Standards & Technology, Electronics & Electrical Engineering Laboratory, Boulder, CO

Conventional superconducting circuit Materials perspective tunnel barrier insulator wiring substrate SubstrateSi/SiO X Thermal WiringNb or AlSputtered InsulatorSiO X CVD BarrierAlO X Thermal Traditional

Conventional materials are used for a lot of really good reasons… Si substrate with thermal a-SiO X on top –Smooth, standard lithography, inexpensive Nb or Al wiring – sputter deposit, polycrystalline –Low temperature, smooth, relatively high T C a-SiO X insulators – CVD –Smooth (no pinholes), low T, easy a-AlO X tunnel barrier – thermal or plasma oxidation –Smooth, no pinholes, low T, easy, self-limiting “CMOS compatible” Need strong motivations for change …

Phase qubit Rabi oscillation Martinis, et. al PRL95, (2005) (SiOX insulator on Si/SiOx substrate) (SiN insulator on sapphire substrate)

New directions tunnel barrier insulator wiring substrate SubstrateSapphire (Al 2 O 3 ) CrystallineExpensive, difficult to work with, can be atomically rough WiringRe, Al/RuAnnealedComplicated, hard to prepare, Hi-T InsulatorSiN, a-Si, Al 2 O 3 Sputtered Epitaxial High T, adhesion, processing Homogeneity, rough BarrierAl 2 O 3 EpitaxialHigh T, homogeneity, rough Materials Difficulties CMOS

Outline Motivations for change –a-SiO X in substrate & insulators –a AlO X in barriers –Superconducting wiring materials Milestones & goals Recent progress Roadmap

Insert qubit pic here Qubit L Stripline (C-SiO X ) Josephson Junction (L&C) => Measure “Q” of simple LC resonators Qubit has SiO 2 Cap in || with J.J. & around lines SiO X AlO x

Power dependence to parallel plate capacitor resonators  wave resonator L f [GHz] P out [mW] P in lowering Q of the resonator with SiO 2 goes down as power decreases! Parallel plate capacitor resonators w/SiO dielectric C L => Compare to capacitors with vacuum dielectric

=> With & without SiO2 over the capacitor C/2 L Dissipation is in SiO2 dielectric of the capacitor! ~P out Interdigitated capacitor resonators

Power dependence of Q LC for parallel plate capacitors HUGE Dissipation Q decreases with at very low power (where we run qubits) N photons Q LC Explains small T 1 ! L C

TLS bath saturates at high E (power), decreasing loss Schickfus and Hunklinger, 1975 Two-level systems in a-SiO2 E d SiO 2 - Bridge bond Amorphous material has all barrier heights present High E Low E

~T R SiO2 =2.1k  Temperature Dependence of Q Q also decreases at low temperature!

Problem - amorphous SiO 2 Why short T 1 ’s in phase Josephson qubits? Dissipation: Idea - Nature: At low temperatures (& low powers) environment “freezes out”: dissipation lowers dissipation increases, by 10 – 1000! Change the qubit design:  find better substrates  find better dielectric & minimize insulators in design

Common insulator/substrate materials SiO X –Bridge bond, unstable Amorphous films have uncompensated O -, H, OH - Si 3 N 4 –N has three bonds – more stable Amorphous films, still have uncompensated charges, H 20% H for low T films, ~ 2% H in high T films Al 2 O 3 –Amorphous – high loss, similar to a-SiO2, has H, OH - in film –Single crystal (sapphire) - Very low loss system

Minimize, optimize dielectric & substrate Rabi oscillations > 600 ns !! Sapphire substrate + SiN insulator:

Superconductor - Aluminum I Tunnel junction a- AlO x -OH - Found improvements due to optimized materials in insulators Tunnel barrier materials

Motivations for new tunnel barriers materials Qubit spectroscopy Increase the bias voltage (tilt) Frequency of |0> => |1> transition goes down Splittings Increase bias

Effects of splittings Quench Rabi Oscilations – strong coupling to qubit Rabi oscillations Spectroscopy

Constant splitting density in a-AlO X barriers 13 um 2 junction 70 um 2 junction Smaller area – Fewer splittings, large gaps (strong coupling) Larger area - More splittings, smaller gap (weaker coupling) Density ~ 1/GHz/  m 2  Splittings are randomly distributed  Use small junctions with low probability of splitting for test structures (< 1  m 2 ) Steffen, et. al (2006)

Two level systems in junction Amorphous AlO tunnel barrier Continuum of metastable vacancies Changes on thermal cycling Resonators must be 2 level, coherent with qubit! I

What we need: Crystalline barrier  -Al 2 O 3 Poly - Al Existing technology: Amorphous tunnel barrier a –AlO x – OH - No spurious resonators Stable barrier Amorphous Aluminum oxide barrier Spurious resonators in junctions Fluctuations in barrier Silicon amorphous SiO 2 Low loss substrate Design of tunnel junctions SC bottom electrode Top electrode

Q: Can we prepare crystalline Al 2 O 3 on Al? Binding energy of Al AES peak in oxide Annealing Temp (K) AES Energy of Reacted Al (eV) Al in sapphire Al Metallic aluminum Aluminum Melts Å AlO x on Al (300 K + anneal) 10 Å AlO x on Al (exposed at elevated temp.)  Anneal the natural oxides  Oxidize at elevated temp. A: No – need high temperature bottom wiring layer

Motivations – New wiring materials Conventional Al, Nb: –Surface oxides with spin polarized traps 1/f flux noise, dephasing times, density ~ /m 2 Alternative materials: –Re: resists oxidation, high melting T, hcp lattice => Al 2 O 3, –Al passivated with Re or Ru => resists oxidation Koch, Clark, di Vincenzo (PRL 2007) e - traps Kondo traps Faoro, Ioffe PRB (2007) Coupled TLS McDermott, et. al (2007)

12 Qubit Test Die Layout Bias coil Qubit loop DC-SQUID

Improvement of junctions seen in spectroscopy of 0  1 transition T = 25 mK Amorphous barrier 70  m 2 Epitaxial barrier 70  m 2 Density of coherent splittings reduced by ~5 in epitaxial barrier qubits

T 1 = ns  best for SiO 2 insulator Splitting density –~3-5 times lower than amorphous barrier of same area Future plan: –advanced wiring dielectrics – SiN, a-Si – 1  s T 1 ? –Use to test wiring layer Min-SiO 2 Epitaxial Re/Al 2 O 3 /a-Al Qubit

Source of Residual TLFs: Al-Al 2 O 3 interface? Electron Energy Loss Spectroscopy (EELS) from TEM shows 1.Sharp interface between Al 2 O 3 and Re 2.Noticeable oxygen diffusion into Al from Al 2 O 3 1.Indicates presence of a-AlO x at interface 2.Will “heal” pinholes Distance (μm) Oxygen content Al 2 O 3 White is oxygen

Need to improve top barrier interface! Interfacial effect ~1 in 5 oxygens at Al interface Agrees with reduced splitting density ~1.5 nm epi-Re interface non-epi Al interface Oxygen Re Al a-AlO x

Al/a-AlO/AlRe/c-AlO/AlRe/c-MgO/Al a: Amorphous c: Crystalline Supports conclusion that Al top electrode “heals” pinholes substrate Al top electrode Tunnel barrier Bottom electrode Top electrode matters Al top electrode always gives good I/V

Re/c-AlO/Re substrate Re top electrode Tunnel barrier Bottom electrode => Pinholes in tunnel barrier Re on top makes JJ leaky

Electrical Testing Summary & Comparison Phase qubits Materials Wiring & barrier InsulatorT 1 (ns) T 2 * (ns) Splitting density (N/GHz/mm2) Reference Al/AlO x /Al 1  m 2 w/shunting C min-SiN x (160) 1Steffen - tomography PRL Al/AlO x /Al 13  m 2 min-SiN x Martinis Dielectric loss PRL Al/AlO x /Almin-SiO 2 170*1Simmonds 2005 Re/Al 2 O 3 /Al epi-junctionmax-SiO PRB qubit - Re/Al 2 O 3 /Al 49  m 2 max-SiO *0.2Submitted APS08 12 qubit - Re/Al 2 O 3 /Al 49  m 2 min-SiO Submitted APS08 12 qubit – Re/MgO/Al New results

Goals 1.Inter-laboratory compatibility –Infrastructure - 6”-wafer chamber for epitaxial trilayers Develop 6” substrate capability Re/Al 2 O 3 /Al, Re/Al 2 O 3 /Re –Supply samples to flux qubit, 6” wafer fabrication facililty 2.Extend work on epitaxial tunnel barriers to flux qubits –Continue on barriers at chip level Chip level –Develop JJ and qubit circuits compatible w/flux qubits –study fully epitaxial systems 3.Study new materials for wiring layers –Al/Ru capping with anneal –Push to understand flux noise and wiring surfaces

Progress 1.Chamber specifications & purchasing – RFQ out –6” wafer capability –Sputtering (Al, Re, Al2O3), k-cell & oxygen reactor –High temperature sample anneal –RHEED, in-situ ellipsometer 2.Sub-micron junction designs –Collaborate with MIT-LL – Will Oliver –Compatible test structures –Optical lithography with vias to junctions –Cl-etch capability at NIST online soon

Progress (continued) 3.SQUID design to test 1/f flux noise –Collaborate with UW, Madison, Rob McDermott –Fabricate SQUIDS using small junction & Cl etch

Impact on roadmap Version 2.0 April 2, 2004, Terry Orlando 1.Scalable systems with Rabi/Ramsey oscillations 2.Ability to Initialize qubits 3.Long (relative) decoherence times, much longer than the gate-operation time 1.Calculations suggest the relaxation times ~ milliseconds. 2.Experimental measurements show at present a lower bounds 1.1–10 μs for the Relaxation time 2.0.1–0.5 μs for the dephasing time![2,3,7–9,11]. 3.Charge, flux, and critical-current noise are probably a technological and materials processing problem![2,3,7–9,11]. 4.The non resonant upper levels: in principle the effects of these levels can be compensated by a pulse sequence which allows the system to act as an effective two level system! 5.Experiments have demonstrated about a thousand gate operations prior to decoherence!. 4.Universal set of quantum gates 5.Qubit specific measurement capability 6.Interconvert stationary and flying qubits 7.Ability to faithfully transmit flying qubits

“Medium” K dielectrics? Si SiN Al 2 O 3 MgO Diamond ZrSiO CaO SiC  Need to use thicker insulators “low” K dielectrics? doped SiOx (F, C Porous SiOx Spin-on polymers (HSQ) Probably not new Other potential new insulators – from VLSI world?