Physical Limits of Computing Dr. Mike Frank CIS 6930, Sec. #3753X Spring 2002 Lecture #25 Limits on Adiabatics: Friction, Leakage, & Clock/Power Supplies Fri., Mar. 15

Administrivia & Overview Don’t forget to keep up with homework!Don’t forget to keep up with homework! –We are  8 out of 14 weeks into the course. You should have earned  ~57 points by now.You should have earned  ~57 points by now. Course outline:Course outline: –Part I&II, Background, Fundamental Limits - done –Part III, Future of Semiconductor Technology - done –Part IV, Potential Future Computing Technologies - done –Part V, Classical Reversible Computing Adiabatic electronics & CMOS logic families, - last Mon. & WedAdiabatic electronics & CMOS logic families, - last Mon. & Wed Limits of adiabatics: Friction,Leakage,Power supplies. Fri.,TODAYLimits of adiabatics: Friction,Leakage,Power supplies. Fri.,TODAY RevComp theory I: Emulating Irreversible Machines - TODAYRevComp theory I: Emulating Irreversible Machines - TODAY RevComp theory II: Bounds on Space-Time Overheads - Wed. 3/20RevComp theory II: Bounds on Space-Time Overheads - Wed. 3/20 Physics-based models of computing - Fri. 3/22Physics-based models of computing - Fri. 3/22 (plus ~6 more lectures…)(plus ~6 more lectures…) –Part VI, Quantum Computing –Part VII, Cosmological Limits, Wrap-Up

Limits of Adiabatics II: Leakage (wrap-up)

Leakage in CMOS (See transparencies - not electronic yet.)(See transparencies - not electronic yet.) In a given technology with constant-field scaling, leakage becomes worse at small scales because:In a given technology with constant-field scaling, leakage becomes worse at small scales because: –Energy barriers between states are lower Higher rates of thermally-induced leakage, at given THigher rates of thermally-induced leakage, at given T Higher rates of quantum tunnelling (temp.-independent)Higher rates of quantum tunnelling (temp.-independent) –Energy barriers between states are narrower Higher rates of quantum tunnellingHigher rates of quantum tunnelling –These effects get worse exponentially with 1/length (doubly-exponentially with time) Need alt. technologies w. high energy barriers!Need alt. technologies w. high energy barriers!

Future Techs. w. Low Leakage? How can achieve low entropy coefficients in minimum-scale (atomic-scale) devices?How can achieve low entropy coefficients in minimum-scale (atomic-scale) devices? –Need high energy barriers: Can achieve with atomic (not just electronic) interactions:Can achieve with atomic (not just electronic) interactions: –E.g. mechanical logics (rod logic, buckling logic) –If strong bonds (e.g. C-C) are used in structure, rates of unwanted bond breakage can made be very low. –Rate for an atom passing through another one (e.g. knobs in rod logic) is extremely low due to »height of barrier: strength of Coulombic & fermionic repulsion between electrons, & »width of barrier: large number of particles involved Other possibilities?Other possibilities?

Limits of Adiabatics III: Clock/Power Supplies See transparencies.

Timing in Adiabatic Systems When multiple adiabatic devices interact, the relative timing must be precise, in order to ensure that adiabatic rules are met. There are two basic approaches to timing:There are two basic approaches to timing: –Global (a.k.a. clocked, a.k.a. synchronous) timing Approach in nearly all conventional irreversible CPUsApproach in nearly all conventional irreversible CPUs Basis for all practical adiabatic/quantum computing mechanisms proposed to dateBasis for all practical adiabatic/quantum computing mechanisms proposed to date –Local (a.k.a. self-timed, a.k.a. asynchronous) timing Implemented in a few commercial irreversible chips.Implemented in a few commercial irreversible chips. Feynman ‘86 showed a self-timed serial reversible computation was implementable in QM, in principleFeynman ‘86 showed a self-timed serial reversible computation was implementable in QM, in principle Margolus ‘90 extended this to a 2-D model with 1-D of parallelism. - Will it work in 3-D?Margolus ‘90 extended this to a 2-D model with 1-D of parallelism. - Will it work in 3-D?

Global Timing Examples of adiabatic systems designed on the basis of global, synchronous timing:Examples of adiabatic systems designed on the basis of global, synchronous timing: –Adiabatic CMOS with external power/clock rails –Superconducting parametric quantron (Likharev) –Adiabatic Quantum-Dot Cellular Automaton (Lent) –Adiabatic mechanical logics (Merkle, Drexler) –All proposed quantum computers But, a problem: Synchronous timing may not scale!But, a problem: Synchronous timing may not scale! –Work by Janzig & others raises issues of possible limits due to quantum uncertainty. Unresolved.

Clock/Power Supply Desiderata Requirements for an adiabatic timing signal / power supply:Requirements for an adiabatic timing signal / power supply: –Generate trapezoidal waveform with very flat high/low regions Flatness limits Q of logic.Flatness limits Q of logic. Waveform during transitions is ideally linear,Waveform during transitions is ideally linear, –But this does not affect maximum Q, only energy coefficient. –Operate resonantly with logic, with high Q. Power supply Q will limit overall system QPower supply Q will limit overall system Q –Reasonable cost, compared to logic it powers. –If possible, scale Q  t (cycle time) Required to be considered an adiabatic mechanism.Required to be considered an adiabatic mechanism. May conflict w. inductor scaling laws!May conflict w. inductor scaling laws! At the least, Q should be high at leakage-limited speedAt the least, Q should be high at leakage-limited speed (Ideally, independent of t.)

Supply concepts in my research Superpose several sinusoidal signals from phase-synchronized oscillators at harmonics of fundamental frequencySuperpose several sinusoidal signals from phase-synchronized oscillators at harmonics of fundamental frequency –Weight these frequency components as per Fourier transform of desired waveform Create relatively high-L integrated inductors via vertical, helical metal coilsCreate relatively high-L integrated inductors via vertical, helical metal coils –Only thin oxide layers between turns Use mechanically oscillating, capacitive MEMS structures in vacuo as high-Q (~10k) oscillatorUse mechanically oscillating, capacitive MEMS structures in vacuo as high-Q (~10k) oscillator –Use geometry to get desired wave shape directly

Early supply concepts Inductors & switches.Inductors & switches. –See transparency. Stepwise charging.Stepwise charging. –See transparency.

Newer Supply Concepts Transmission-line-based adiabatic resonators.Transmission-line-based adiabatic resonators. –See transparency. MEMS-based resonant power supplyMEMS-based resonant power supply –See transparency, & next slide Ideal adiabatic supplies - Can they exist?Ideal adiabatic supplies - Can they exist? –Idealized mechanical model: See transparency. –But, may be quantum limits to reusability/scalability of global timing signals. This is a very fundamental issue!This is a very fundamental issue!

A MEMS Supply Concept Energy stored mechanically.Energy stored mechanically. Variable coupling strength -> custom wave shape.Variable coupling strength -> custom wave shape. Can reduce losses through balancing, filtering.Can reduce losses through balancing, filtering. Issue: How to adjust frequency?Issue: How to adjust frequency?

Summary of Limiting Factors When considering adiabaticizing a system: What fraction of system power is in logic? f LWhat fraction of system power is in logic? f L –Vs. Displays, transmitters, propulsion. What fraction of logic is done adiabatically? f aWhat fraction of logic is done adiabatically? f a –Can be all, but w. cost-efficiency overheads. How large is the I on /I off ratio of switches?How large is the I on /I off ratio of switches? –Affects leakage & minimum adiabatic energy. What is the Q sup of the resonant power supply?What is the Q sup of the resonant power supply? What is the relative cost of power & logic? r $What is the relative cost of power & logic? r $ –E.g. decreasing power cost by r $ by increasing HW cost by  r $ will not help. “Power premium”

Min. energy & R off /R on ratio Note that: c E = C 2 V 2 R on and if dominant leakage is source/drain: P leak = V 2 /R offNote that: c E = C 2 V 2 R on and if dominant leakage is source/drain: P leak = V 2 /R off So: c E P leak = C 2 V 4 /(R off /R on ) E min = 2(c E P leak ) 1/2 = 2CV 2 (R off /R on )  1/2So: c E P leak = C 2 V 4 /(R off /R on ) E min = 2(c E P leak ) 1/2 = 2CV 2 (R off /R on )  1/2 So: Q max = ½CV 2 / (2CV 2 (R off /R on )  1/2 ) = ¼(R off /R on ) 1/2 = ¼(I on /I off ) 1/2So: Q max = ½CV 2 / (2CV 2 (R off /R on )  1/2 ) = ¼(R off /R on ) 1/2 = ¼(I on /I off ) 1/2

Minimizing cost/performance $ P = Cost of power in original system$ P = Cost of power in original system $ H = Cost of logic HW in original system$ H = Cost of logic HW in original system $ P = r $ $ H ; $ H = $ P /r $$ P = r $ $ H ; $ H = $ P /r $ For cost-efficiency inverse to energy savings:For cost-efficiency inverse to energy savings: $ tot,min = $ P r $ -1/2 + $ H r $ 1/2 = 2 $ P r $ -1/2$ tot,min = $ P r $ -1/2 + $ H r $ 1/2 = 2 $ P r $ -1/2 $ tot,orig = $ P + $ H = (1+r $ )$ H = ((1+r $ )/r $ ) $ P$ tot,orig = $ P + $ H = (1+r $ )$ H = ((1+r $ )/r $ ) $ P $ tot,orig /$ tot,min = ½(1+r $ )r $ -1/2  ½r $ 1/2 for large r $$ tot,orig /$ tot,min = ½(1+r $ )r $ -1/2  ½r $ 1/2 for large r $

Summary of adiabatic limits Cost-effective adiabatic energy savings factor:Cost-effective adiabatic energy savings factor: S a = E conv / E adia in cost-effective adiabatic system Some rough upper bounds on S a : S a  ~ 1/(1  f L ) S a  ~ 1/(1  f a ) S a  ~ ¼(I on /I off ) 1/2 S a  Q sup S a  ~ r $ 1/2 (worse for non-ideal apps)Some rough upper bounds on S a : S a  ~ 1/(1  f L ) S a  ~ 1/(1  f a ) S a  ~ ¼(I on /I off ) 1/2 S a  Q sup S a  ~ r $ 1/2 (worse for non-ideal apps) Discussion ignores benefits from adiabatics of denser packing & smaller communications delays in parallel algorithms. (More later.)Discussion ignores benefits from adiabatics of denser packing & smaller communications delays in parallel algorithms. (More later.)

Reversible Computing Theory I: Reversible Logic Models

Reversible Logic Models It is useful to have a logic-level (Boolean) model of adiabatic circuits.It is useful to have a logic-level (Boolean) model of adiabatic circuits. Can model all logic using pipelinable logic elements that consume their inputs.Can model all logic using pipelinable logic elements that consume their inputs. –Warning: In such models Memory requires recirculation! This is not necessarily more energy- efficient in practice than retractile (non-input consuming) approaches! There is a need for more flexible logic models.There is a need for more flexible logic models. If inputs are consumed, then input  output logic function must be invertible.If inputs are consumed, then input  output logic function must be invertible.

Input-consuming inverter: Before:After: inoutinout E.g. SCRL implementation: in out Input arrow indicates input data is consumed by element.

Input-consuming NAND gate: Before:After: A BoutA Bout Input-consuming NAND gate: Before:After: A BoutA Bout No implementation in SCRL (or any fully adiabatic style) as a stand-alone, pipelined logic element!No implementation in SCRL (or any fully adiabatic style) as a stand-alone, pipelined logic element! An Irreversible Consuming Gate A B out 4 possible inputs, 2 possible outputs. At least 2 of the 4 possible input cases must lead to dissipation!

NAND w. 1 input copied? Still not invertible:BeforeAfter A B A’ out A B A’ out Still not invertible:BeforeAfter A B A’ out A B A’ out A B out A’A’

Reversible Computing Theory II: Emulating Irreversible Machines