1 Passive Distortion Compensation for Package Level Interconnect Chung-Kuan Cheng UC San Diego Dongsheng Ma & Janet Wang Univ. of Arizona

2 Outline 1.Motivation 2.Review of High-Speed Serial Links 3.Passive Distortion Compensation 1.Theory 2.Implementation 3.Simulation Results 4.Power Management and System Integration 5.Research Direction

3 1. Motivation: ITRS Bandwidth Projection Abundant on-chip bandwidth Off-chip bandwidth is the bottleneck Many chip are I/O limited Technology (nm) Normalized unit to 90nm node Courtesy of Hamid Hatamkhani et al., DAC ‘06

4 2. Review of High-Speed Serial Links TechniquesOn-ChipOff-Chip Pre-emphasis and equalization √√ Clocked Discharging (M. Horowitz, ISVLSI’03) √ Frequency Modulation (S. Wong, JSSC ’03; Jose ISVLSI ’05) √√ CDMA on wireline (Jongsun Kim et al.) √√ Non-linear Transmission Line (E. Hajimiri JSSC’05, E.C. Kan CICC ’05) √ Resistive Termination (Tsuchiya et al., EPEP; M. Flynn ICCAD ’05) √√

5 3. Passive Distortion Compensation Typical RLC Transmission Line Distortionless Transmission Line Frequency dependent phase velocity (speed) and attenuation Intentionally make leakage conductance satisfy R/G=L/C Frequency response becomes flat from DC mode to Giga Hz

6 3.1 Theory: Telegrapher’s Equations Telegrapher’s equations Propagation Constant Wave Propagation and correspond to attenuation and phase velocity. Both are frequency dependent in general. Characteristic Impedance

7 3.1 Theory: Distortionless Lines Distortionless transmission line If Both attenuation and phase velocity become frequency independent

8 3.1 Theory: Differential Case Common Mode – Current flowing in the same direction Differential Mode – Current flowing in the opposite direction Shunt between each line to groundShunt between the two lines

9 3.2 Implementation Evenly add shunt resistors between the signal line and the ground Non-ideality Ideal AssumptionIn PracticeImplication Homogeneous and distributive line Discrete shunts What’s the optimal spacing? Are the shunt resistors realizable? Frequency independent RLGC Frequency dependent RLGC What’s the optimal frequency for the matching?

Implementation: MCM trace MCM On-chip Length Series Resistance Frequency dependency of line parameters Large Small ~10 cm ~ 10 mm 1 Ω/mm 1 Ω/μm MCM trace vs. On-chip interconnect Operation regionRLC RC

Implementation: A MCM Stripline Case Control the signal line thickness to minimize skin effect (cost vs. distortion) Assume LCP dielectric Geometry based on IBM high-end AS/400 system

Simulation: Methodology Transient simulation in Hspice Each transmission line segment is modeled by W- element using frequency-dependent tabular model Discrete resistors Used CZ2D tool from IBM for RLGC extraction Part of IBM EIP (Electrical Interconnect & Packaging) suite. Fast and accurate Ensures causality of transient simulation

Simulation: RLGC vs. Frequency R C Match at DC Boost up low frequency traveling speed Balance low frequency attenuation and high frequency attenuation Z0 = 78 Ω, delay = ps/cm R 1MHz =11.07 Ω/cm, L 1MHz =5.52e-3 μH/cm, C 1MHz =0.74 pF/cm R shunt =L 1MHz /R 1MHz C 1MHz = Ω/cm L G

Simulation: Shunt Resistor Spacing Number of shunt resistors = N Resistors are implemented with embedded carbon paste film Spacing depends on the target data rate

Attenuation W8μm/t2μm/b20μm

Phase Velocity W8μm/t2μm/b20μm

Simulation: Pulse Response less severe ISI effect DC saturation voltage determined by the resistor ladder

Jitter and Eye opening for 2um case 10 cm20 cm Jitter (ps)Eye opening (volt)Jitter (ns)Eye opening (volt) 1 shunt/1 cm Terminated with Z Terminated with Rdc Open end > 70< 0.14 W8μm/t2μm/b20μm 1.Each shunt resistor is ohm 2.Z 0 =78 ohm 3.For 10cm line, R dc = 66.9 ohm; for 20 cm line, R dc =33.5 ohm

Jitter and Eye opening for 4.5um case 10 cm20 cm Jitter (ps)Eye opening (volt)Jitter (ns)Eye opening (volt) 1 shunt/1 cm Terminated with Z Terminated with Rdc Open endUnrecognizable W8μm/t4.5μm/b20μm 1.Each shunt resistor is 1232 ohm 2.Z 0 =71.1 ohm 3.For 10cm line, R dc = ohm; for 20 cm line, R dc =61.6 ohm

Simulation: Eye Diagrams With 10 shunts (each = 669.5) Without shunt resistors Jitter = 22.5 ps Eye opening = 0.51 V Jitter = 5.57 ps Eye opening = V W8μm/t2μm/b20μm/L10cm 1000 bit PRBS at 10Gbps W-element + tabular RLGC model in HSpice Clear eye opening Reduced amplitude

Best Eye Diagram for 2um thick case W8μm/t2μm/b20μm/L10cm, 10 distributed resistors Jitter & eye opening v.s. shunt value Best case when each shunt is 500 ohm Jitter = 4.63 ps Eye opening = V Jitter Eye opening

22 Best eye diagram when only terminator is used, 2um thick case Jitter Eye opening W8μm/t2μm/b20μm/L10cm, terminator only Jitter & eye opening v.s. R_term Best case when terminator 90 ohm Jitter = 4.97 ps Eye opening = V

23 W8μm/t2μm/b20μm/L20cm, 20 distributed resistors Jitter & eye opening v.s. shunt value Best case when each shunt is 600 ohm Jitter = ps Eye opening = V Jitter Eye opening

24 W8μm/t2μm/b20μm/L20cm, terminator only Jitter & eye opening v.s. R_termBest case when terminator 40 ohm Jitter = ps Eye opening = V Jitter Eye opening

Eye Diagram for 4.5um thick case when matched at DC Sleepy Eye Jitter = 22.8 ps eye opening = V W8μm/t4.5μm/b20μm/L10cm Open ended10 shunts matched at DC

Best Eye Diagram for the 4.5um thick case W8μm/t4.5μm/b20μm/L10cm, 10 distributed resistors Jitter & eye opening v.s. shunt value Best case when each shunt is 500 ohm Jitter = ps Eye opening = V Jitter Eye opening

27 W8μm/t4.5μm/b20μm/L10cm, terminator only Jitter & eye opening v.s. R_term Best case when the terminator is 80 ohm Jitter = 7.18 ps Eye opening = V Jitter Eye opening

28 W8μm/t4.5μm/b20μm/L20cm, 20 distributed resistors Jitter Eye opening Jitter & eye opening v.s. shunt value Best case when each shunt is 800 ohm Jitter = ps Eye opening = V

29 W8μm/t4.5μm/b20μm/L20cm, terminator only Jitter Eye opening Jitter & eye opening v.s. R_term Best case when the terminator is 110 ohm Jitter = ps Eye opening = V

Eye Diagram for the MCM trace Jitter = ps Eye opening = Jitter = ps eye opening = V W8μm/t4.5μm/b20μm/L20cm Terminated with Z 0 20 shunts matched at DC

31 4. Adaptive Power Management (APM) The distortionless signaling simplifies the interface circuitry. However, the twice heavier attenuation due to passive compensation calls for adaptive power management; With adaptive power management, we adaptively regulate the power supply of the transmitter according to attenuation; The regulated supply voltage guarantees the speed of transmission while keeping the minimal power overhead and well-controlled bit-error rate.

32 4. APM Preliminary Results

33 4. APM Controller

34 4. System Integration The reduction of the jitter leaves larger design margin for interface circuit design; To enable an effective and accurate communication, the operation of transmitter and receiver must be well synchronized. This requires accurate clock positioning and phase locking; Synergic method will be taken to achieve mutual compensation and joint leverage on signal accuracy, attenuation and system power.

35 5. Research Direction Develop analysis models for the technology Eye diagram analysis via step responses Power consumption Optimize technologies Chip carrier and board technologies Redistribution Physical dimensions Shunts, terminators Prototype fabrication & measurement More applications: clock trees, buses Incorporate transmitter/receiver design

36 Remark Distortion Compensation: Source termination: Impedance Receiver termination: Voltage Clamp, Matched Z, Optimized Z. Distributed shunts Combination of above techniques Packaging Current Products: Improve signal quality based on current fabrication technologies. Future Products: Devise the optimal combination.

37 The End Thank you!