MICAS Department of Electrical Engineering (ESAT) AID–EMC: Low Emission Digital Circuit Design Junfeng Zhou Wim Dehaene Update of the “Digital EMC project” September 2nd, 2005

MICAS Department of Electrical Engineering (ESAT) Outline of presentation Outline: Low noise logic families Comparison Conclusion Low noise Power Supply circuit Principles Switching mode Continuous mode Conclusion Questions on the test chip

MICAS Department of Electrical Engineering (ESAT) Problem with CSL and C-CBL CSL: rather slow power hungry low logic swing C-CBL: Bad process variation behaviour sizing for optimal current balance is really difficult Fig.1 CSL inverter Fig.2 C-CBL inverter

MICAS Department of Electrical Engineering (ESAT) Solution- Enhanced current steering logic Still current source basing Increase in logic level, hence increase the robustness Reduced output capacitance, hence the speed is increased Fig.3 E-CSL inverter

MICAS Department of Electrical Engineering (ESAT) Comparison of CSL, C-CBL, ECSL and SCMOS Fig.5 di/dt vs. frequencyFig.4 power vs. frequency

MICAS Department of Electrical Engineering (ESAT) di/dt performance vs. process variation Fig.6 di/dt vs. process corner

MICAS Department of Electrical Engineering (ESAT) Comparison of 16-bit RCA Fig.7 power vs. frequency Fig.8 di/dt vs. frequency

MICAS Department of Electrical Engineering (ESAT) Conclusion of low noise logic families Current source ensures the major di/dt reduction, Process variation sensitivity also becomes better due to the dominance of current source, E-CSL gives comparable di/dt performance with CSL, E-CSL is Faster and Less power consumption than CSL due to the lower area and lower capacitance. Winner is E-CSL

MICAS Department of Electrical Engineering (ESAT) Problems and proposal However 2 problems still remain: Static power consumption New logic family standard cell must be designed and characterised ?? Is there any global approach ??

MICAS Department of Electrical Engineering (ESAT) Principles of low noise power supply Fig.9 Diagram of Low noise power supply 1.Current source ensures the major di/dt reduction 2.Do not give more current the circuit needs, i.e. minimize the static current 3. Slow varying is key to EMC success

MICAS Department of Electrical Engineering (ESAT) Option 1- Switching mode power delivery Fig.10 Switching mode power delivery system Determine the switching speed, hence determine the di/dt Energy reservoir when slow Switching

MICAS Department of Electrical Engineering (ESAT) Functionality verification of option 1 Fig.11 Function simulation of the switching mode power supply circuits 12v supply current 12v supply current di/dt Out_0 Out_1 Out_2 VDD_input 9v 8v 7v

MICAS Department of Electrical Engineering (ESAT) Comparison with standard CMOS Fig.12 di/dt and FFT comparison with standard CMOS 3.3v supply current w/o SW 12v supply current 12v supply current di/dt, P-P= 5.0e7 A/s 3.3v supply current di/dt w/o SW, P-P= 1.51e11 A/s 105 times= 40dB

MICAS Department of Electrical Engineering (ESAT) Option 2- Continuous mode power delivery Fig.13 Continuous time power delivery system continuous time OTA feedback loop stable Still under investigation Determine the switching speed, Hence determine the di/dt Energy reservoir when slow Switching

MICAS Department of Electrical Engineering (ESAT) Functionality Simulation of option 2 Fig.14 Functionality simulation of continuous time power delivery system continuous time OTA feedback loop stable 12v supply current 12v supply current di/dt Vcontrol VDD_input 9v 2 nd order under damped behaviour, still under study

MICAS Department of Electrical Engineering (ESAT) Comparison with standard CMOS Fig.15 di/dt and FFT comparison with standard CMOS 3.3v supply current w/o CT 12v supply current 12v supply current di/dt, P-P= 1.0e7 A/s 3.3v supply current di/dt w/o CT, P-P=1.51e11 A/s 162 times= 44dB

MICAS Department of Electrical Engineering (ESAT) Conclusion of low noise power supply Both approaches give comparable simulation results, Both approaches have potential stability problem as in any feedback loop, Switching mode : easy design, Continuous mode : more difficult to design but potentially has better di/dt suppression.

MICAS Department of Electrical Engineering (ESAT) What is the next step Figure out current behaviour of a typical AMIS digital block Decide between switching mode and continuous mode: more simulation required theory of stability to be analyzed further Test chip in I3T80

MICAS Department of Electrical Engineering (ESAT) Proposal Test chip Proposal: 1. Can we get a series regulator ? (for example, 12V  3.3V ) 2. Test structure for low noise logic families and/ or

MICAS Department of Electrical Engineering (ESAT) Questions Thank you for your attention