DAQ+trigger operation during 2008 run D. Nicolò University of Pisa & INFN, Pisa

October 23, Outlook DAQ –Data throughput & storage –Additional features –The slow control & alarms Trigger –Selection criteria –Efficiency & background rejection –Rates & Livetime DRS system –DRS2/3 performances –DRS4 design Improvements for 2009 run DAQ+Trigger operation

DAQ

Data throughput and storage Event & data rate –6.5 ev/s, ~ 9 MB/s run) –max. 30 ev/s (limited by VME readout & DRS2 calibration) current %Live ~ 80% Data write to online disk –2000 events/run ~ 3 GB file size ( smaller for calibration runs) –occupancy ~ 1 TB/d 100 TB/y (to be offline suppressed x3) –Disk available with 2TB capability buffer for 2 days Data storage & monitoring –Lazy Logger process to automatic copy to offline cluster ( total 100 TB HD) –gzip Midas data files (x0.5 compression) –Offline histos available soon afterwards ( ~ 10 min after Run stop) October 23, 2015 DAQ+Trigger operation 4

Offlinecheck: an example October 23, 2015 DAQ+Trigger operation 5

DAQ features Automatic stop –Maximum event number completion data size Run batch to be started from shell –Runsubmit xml script –Run parameters (#events, trigger operation, …) loaded to the online database (ODB) System running smoothly Major troubles –Event “mismatch” –FE hangs up –FE still busy at run start October 23, 2015 DAQ+Trigger operation 6

MSCB slow control October 23, 2015 DAQ+Trigger operation 7 13 Ethernet “Submasters” 8 SCS-2000 units each with up to 64 I/O Control of detector behaviour Newly added features Separator HV Beam shutter (beam on-off) Data recorder in the MIDAS history files available through the WEB page Alarm generation in the case of failures

Trigger

PSI - Jul. 18th, Selection criteria QT H QT L MeV DW W DW N  -energy e + -  direction e + -  timing trig.# name conditions 0 MEG Q SUM > QT H && D < D N && |  T| < TW N 1 MEG-Q Q SUM > QT L && D < D N && |  T| < TW N 2 MEG-D Q SUM > QT H && D < D W && |  T| < TW N 3 MEG-T Q SUM > QT H && D < D N && |  T| < TW W 4 RD-narrowQ SUM > QT L && |  T| < TW N 5 RD-wide Q SUM > QT L && |  T| < TW W

October 23, All triggers can be: masked pre-scaled (up to 32 bits) and mixed in the DAQ (see above) Additional features Additional pieces of information 100 MHz, 1.28  s depth, 10 bits, waveforms for all channels  standalone, backup DAQ system Single channel rate (identification of hot/dead channels) Proton current Scalers for rate measurements Event Counter (hardware distributed to the DRS boards) Trigger pattern (hardware distributed to the DRS boards) Live and Dead Time DAQ+Trigger operation

October 23, On-line E γ resolution σ = 3.8% 45 MeV threshold  from signal) 55 MeV γ -line from π 0 -decay

October 23, E γ efficiency Obtained from the ratio S H (E γ )/S L (E γ ) off-line energy spectra normalizated by using proton current info DAQ+Trigger operation Threshold smearing mainly due to on-line energy resolution ε  99% 0.5 counts/s/MeV FWHM = 9,4% at 45 MeV

October 23, Δ t e γ efficiency |Δ T (LXe-TC)| < 10 ns Spectrum expected to be flat (accidental background) σ( Δ T) = (3.8 ± 0.1) ns ε Δ T ~ 99% (σ t = 2.5 ns on each) DAQ+Trigger operation B(p,  )C (background free!) Δ t (ns) –online –offline TRG type 0 signal

October 23, e + - γ direction - γ -position by max PMT in LXe -e + -position by charge asymmetry in TC (TC fibers not included yet) –association LUT based on MC Cross-check with the data (Radiative Decay sample) a) Search for e + “good quality” track candidates ( χ 2, matched extrapolation to TC) b) Track a backward hypothetical γ from decay vertex; c) γ hit position  LXe PMT index; d) LXe PMT index  search for e + -hit on TC in the LUT DAQ+Trigger operation Work in progress

DRS

DRS in 2008 DRS2 –All analog channels equipped 848 LXe PMTs 60 TC PMTs 1728 DC (anode + vernier) 0.5 – 1.6 GHz sampling speed –Voltage non-linearity calibration in FE –Temperature dependence 1.4%/ o C DRS3 –4 cards available NIM TC DTD outputs –Voltage linearity (0 : 1 V) –Ghost pulse problem to be fixed in DRS4 October 23, 2015 DAQ+Trigger operation 16

DRS2 linearity Cell-dependent non-linear response function applied Differential linearity restored at 2% October 23, 2015 DAQ+Trigger operation 17 TRG amplitude DRS amplitude

Timing Test done by splitting the same TC pulse to 2 channels of the same chip Plot of (t 0 -t 1 )/2 negligible with respect to detector resolution Different domino waves running on different chips chip-to-chip timing needs calibration critical issue October 23, 2015 DAQ+Trigger operation 18 rms = 6.6 psrms = 9.4 ps DRS2DRS3

DRS4 design Same VME board as former versions New mezzanine card –Single ended differential input (common-noise suppression) –Memory doubled (up to 3.2 GHz sampling or 2x wider time window) –All domino waves running synchronously (ref. CLK jitter < 10 ps) –New DC supply at 2.5 V compatibility with FPGA LVDS ref. CLK October 23, 2015 DAQ+Trigger operation 19

Sept. 9th, 2008 MEG weekly meeting 20 DRS4 Schedule Add special clock chip for in-situ calibration First prototype DRS4 mezzanine board end of February Extend mezzanine firmware: Store calibration in EEPROM, channel cascading (needed for 3.2 GSPS operation), in-situ timing calibration Test in area (March) with cosmics Start mass production: 5-6 weeks ( end of May) Deploy DRS4 boards in area: June Use July as contingency

Further improvements in 2009 Hardware –Test of the electronics chain by injecting a test pulse from splitter output DAQ –No calibration needed for DRS4 DAQ speed-up Max. rate ev/s, %Live 80% 90% –Reduce dead time (6.5%) due to Start/Stop procedure Subrun –Fix residual troubles Trigger –Optimization of dynamic range might be a concern if LXe light yield increases DRS4 October 23, 2015 DAQ+Trigger operation 21

Backup slides

October 23, System overview 5 crates DRS Hit registers Trigger 4 crates 20 MHz clock start stop sync Trigger signal Event number Trigger type Trigger Busy Error Ancillary system  E5 area ‘cave’ PC (Linux) Front-End PCs Run start Run stop Trigger config Master PC (Linux) Gigabit Ethernet On-line farm PC (Linux) storage PC (Linux) Event builder DAQ+Trigger operation

DAQ scheme October 23, 2015 DAQ+Trigger operation 24 TRG1TRG2TRG3TRG9DRS4DRS5DRS6DRS7DRS8 trigger & trigger type & event # LSB busy internal trigger & busy SYSTEM01SYSTEM02SYSTEM03SYSTEM04SYSTEM05SYSTEM06SYSTEM07SYSTEM08SYSTEM09 Event Builder SYSTEM Logger start sequence stop sequence

25 Event “mismatch” TRG1TRG2TRG3TRG9DRS4DRS5DRS6DRS7DRS8 SYSTEM01SYSTEM02SYSTEM03SYSTEM04SYSTEM05SYSTEM06SYSTEM07SYSTEM08SYSTEM HW event # SW serial # HW event # SW serial # HW event # SW serial # Run stopped, error message returned by Event Builder

boards 14 x 48 Type Inner face (216 PMTs) 2 boards boards 9 x 48 Type Side faces lat. (144x2 PMTs) 4x1 back (216 PMTs) 4x1 u/d (54x2 PMTs) 4x1 1 board Bars (30x2 PMTs) Fibers (512 APDs) 8x1 1 board 2 x48 Type boards 9 x 48 Type boards 1 x 48 Type Wires 64 channels 2 x48 Type1 16 NaI+pre-shower 16 channels The trigger tree Type2 4 x 48 Type1 16 CR counters 32 channels Type board 2 boards START STOP CLK SYNC Synchronous operation at 100 MHz LXe TC DC Aux 1 board

Rate monitor October 23, 2015 DAQ+Trigger operation 27