ECE Lecture 13 Motorola 68HC11

Resources 68HC11 E-series Reference Guide and if necessary 68HC11 E-series Technical Data 68HC11 Reference Manual all available at Optionally: Peter Spasov, Microcontroller Technology, any edition, Prentice-Hall, Chapter 2, Software, and Chapter 7 Clocked Operation (you can borrow this book from the ECE 447 students).

Basic Computer System CPU Memory Program + Data I/O Interface Parallel I/O Device Serial I/O Device Data Bus Address Bus Control Bus Parallel Data Serial Data

Microprocessor - usually memory off-chip and only basic I/O interface on chip e.g., Intel 8008, 8080, 8086, 80286, Pentium Single-chip microcomputer - CPU, memory, I/O interface, and simple I/O devices on one LSI chip e.g., Intel 8048, 8051, Motorola 68HC11, 68HC16

Microcontroller: I/O oriented single-chip microcomputer Microcontroler vs. other single-chip microcomputers: Extended I/O capabilities synchronous and asynchronous communication devices, A/D and D/A converters, timers, counters, watchdogs Interrupt handling increased ability to prioritize levels of interrupts and mask individual interrupts Instruction set instructions oriented toward bit manipulation, operations on single bits of memory words or I/O ports

Early microcroprocessors performance integration General-purpose microprocessors Single-chip microcomputers - small price - low power consumption - built-in memory - built-in I/O devices - high speed - long word size volume sold x 1x 10 (e.g., Pentium, Alpha, Power PC) (e.g., MC68HC11, 8051) (8080, 6800, Z80)

68HC11 Organization

CPU RAM ROM EEPROM TIMER A/D SPI SCI PORT APORT BPORT CPORT DPORT E Organization of MC68HC11 in the Single-Chip Mode 88 (4)

CPU RAM ROM EEPROM TIMER A/D SPI SCI PORT A PORT DPORT E Organization of MC68HC11 in the Expanded Bus Mode 8 (4) EXTERNAL RAM EXTERNAL ROM EXTERNAL EPROM EXTERNAL I/O

Abbreviations CPU - Central Processing Unit := ALU (Arithmetic Logic Unit) + Control RAM - Random Access Memory := Read/Write Memory ROM - Read Only Memory (non-volatile) EPROM - Erasable Programmable ROM EEPROM - Electrically Erasable ROM SCI - Serial Communication Interface (asynchronous serial communication interface) SPI - Serial Peripheral Interface (synchronous serial communication interface) A/D - analog-to-digital converter

Internal Registers

X-index register Y-index register Stack Pointer Program Counter Condition Code Register Register structure of MC6811 Double Accumulator D Accumulators A and B or IX 0 15 IY 0 15 SP 0 15 PC 0 15 CCR 07 D AB S X H I N Z V C

Condition Code Register CCR 0 7 S X H I N Z V C carry / borrow overflow zero negative I-interrupt mask half-carry (from bit 3) X-interrupt mask stop disable

I/O Ports and other I/O Devices

Input/Output Ports Port Input Pins Output Pins Bidirectional Pins Shared Functions Port A Port B Port C Port D Port E 3–––83–––8 38–––38––– 2–86–2–86– Timer High Order Address Low Order Address and Data Bus SCI and SPI A/D Converter

Memory mapped I/O (e.g., Motorola) 0 MAX I/O Control lines: read/write Separate I/O (e.g., Intel) 0 MAX I/O 0 max Control lines: read/write memory/io

Memory map of MC68HC11E1 $0000 $1000 $B600 $FFFF $0000 $1000 $B600 $FFFF EXT $0000-$01FF 512 bytes RAM $1000-$103F 64 bytes I/O registers $B600-$B7FF 512 bytes EEPROM Single-chip modeExpanded bus mode

I/O Device Architecture ….. Control registers instructions ….. Status registers status of the device Data registers ….. I/O device address1/name1 addressN/nameN..... inputs (operands) outputs (results)

Input/Output Register Types 1. Control registers - hold instructions that regulate the operation of internal I/O devices 2. Status registers - indicate the current status of internal I/O devices 3. Data registers - hold the input data sent to the I/O device and output data generated by this device 4. Data direction registers - control the direction (in or out) of the data flow to/from bidirectional data registers

Assembly Language vs. Machine Code

Assembly language vs. machine code Assembly language [label] mnemonic [operands] LDAA #$4A LDAA $5B, Y Machine code $86 $4A [prebyte] opcode [operands] $18 $A6 $5B START CLRA $4F

Number of instructions represented using a single-byte opcode Number of instructions represented using a combination prebyte+opcode Values of prebytes 18, 1A, CD Machine code

; move.s11 ; function that transfer an array of 128 bytes ; starting at location $C800 to the memory area ; starting at location $D800 SECTION.text transfer: LDX #$C800 LDY #$D800 loop_begin LDD 0,X STD 0,Y INX INY CPX #$C880 BNE loop_begin RTS END move.s11

move.lst C:/introl/Examples/E Sep 24 00: Page 1 1 ; move.s11 2 ; function that transfer an array of 128 bytes 3 ; starting at location $C800 to the memory area 4 ; starting at location $D SECTION.text transfer: cec800 LDX #$C ced800 LDY #$D loop_begin ec00 LDD 0,X ed00 STD 0,Y c 08 INX d 08 INX e 1808 INY INY cc880 CPX #$C f0 BNE loop_begin RTS END

C:/introl/Examples/E Sep 24 00: Page 2 Section synopsis ( 24).text C:/introl/Examples/E Sep 24 00: Page 3 Symbol table.text | loop_begin | transfer E C:/introl/Examples/E Sep 24 00: Page 4 Symbol cross-reference.text *6 loop_begin *11 19 transfer *8

Groups of Instructions

Groups of instructions (1) 1. Data handling instructions a. Move instructions (e.g., load, store, exchange) b. Alter data instructions (e.g., clear, increment, decrement) c. Edit instructions (e.g., shift, rotate) 2. Arithmetic instructions (e.g., add, subtract, multiply, divide, negate) 3. Logic instructions (e.g., and, or, xor) 4. Data test instructions (e.g. compare, test, bit test)

5. Control instructions (e.g., jump, branch) Groups of instructions (2) 6. Condition code instructions (e.g., set carry, clear overflow flag) 7. Stack operations (e.g. push, pull) 8. Subroutine-related instructions (e.g. jump to subroutine, return from subroutine) 9. Interrupt-related instructions (e.g. software interrupt, return from interrupt)

Addressing Modes

Move instructions (1) 1. memory  register LDA [A, B] LD [D, X, Y, S] 2. register  memory STA [A, B] ST [D, X, Y, S] 3. register  register TAB, TBA 4. memory  memory IMM, DIR, EXT, IND DIR, EXT, IND INH N Z V C 0 –

Move instructions (2) 1. register  register XGD [X, Y] N Z V C – – INH

Addressing modes of the LDAA instruction Immediate mode LDAA #$5C Direct mode LDAA $1B Extended mode LDAA $6D00 Indexed mode LDAA $56, X LDAA $56, Y $5C  A ($001B)  A ($6D00)  A (IX+$56)  A (IY+$56)  A

Instruction Table

Addressing modes of MC68HC11 (1) 1. Inherent:Opcode contains reference. 2. Immediate: Data follows opcode. 3. “Direct”:Base page, Page 0; Low byte of address follows opcode. High byte of address set to zero. 4. Extended:Direct; Complete address of the operand follows the opcode.

5. IndexedContents of X or Y index register added to the unsigned offset in the byte following the opcode to form effective address 6. Relativesigned byte following the opcode added to the pre-incremented program counter PC to form effective address Addressing modes of MC68HC11 (2)

Arithmetic Instructions

Arithmetic instructions (1) 1. addition Acc + M  Acc ADD [A, B, D] ADC [A, B] 2. subtraction Acc – M  Acc SUB [A, B, D] SBC [A, B] IMM, DIR, EXT, IND N Z V C IMM, DIR, EXT, IND EXT, IND INH 3. negation -X NEG [A, B] NEG

B = b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 Unsigned vs. signed numbers Unsigned number Signed number B = b 7 b 6 b 5 b 4 b 3 b 2 b 1 b weights B = b b b b b b b b =bi2ibi2i  i=0 7 B = b b b b b b b b = - b bi2ibi2i  i=0 6

Definition of the Condition Code Register flags (1) Z = 1 if result = 0 0 otherwise Zero flag - Z N = sign bit of the result r 7 - for 8-bit operands r 15 - for 16-bit operands Negative flag- N zero result negative result

Definition of the Condition Code Register flags (2) C = 1 if result > MAX_UNSIGNED or result < 0 0 otherwise where MAX_UNSIGNED = for 8-bit operands (registers A, B) for 16-bit operands (register D) V = 1 if result > MAX_SIGNED or result < MIN_SIGNED 0 otherwise where MAX_SIGNED = for 8-bit operands (registers A, B) for 16-bit operands (register D) MIN_SIGNED = -2 7 for 8-bit operands (registers A, B) for 16-bit operands (register D) Carry flag - C Overflow flag - V out-of-range for unsigned numbers out-of-range for signed numbers

Overflow for signed numbers (1) Indication of overflow Positive + Positive = Negative Negative + Negative = Positive Formulas Overflow 2’s complement = x k-1 y k-1 s k-1 + x k-1 y k-1 s k-1 = = c k  c k-1

Overflow for signed numbers (2) x k-1 y k-1 c k-1 c k s k-1 overflow c k  c k

Condition code instructions 1. set a flag 1  flag SE [C, V, I] 2. clear a flag 0  flag CL [C, V, I] 3. change all flags A  CC TAP 4. read all flags CC  A TPA

Arithmetic instructions (2) 1. addition Reg + B  Reg ABA AB [X, Y] 2. subtraction A – B  A SBA INH N Z V C INH – –

Arithmetic instructions (3) 1. unsigned multiplication A x B  D MUL 2. unsigned divisionD/IX  IX D mod IX  D IDIV 3. unsigned fractional division D < IX 2 16 D/ IX  IX 2 16 D mod IX  D 4. decimal adjustment DAA INH N Z V C INH – – – – 0 – FDIV INH ?

Extending the number of bits of a signed number x k-1 x k-2 … x 1 x 0 y k’-1 y k’-2 … y k y k-1 y k-2 … y 1 y 0 X Y two’s complement x k-1 x k-1 x k-1...x k-1 x k-2 … x 1 x 0

Other Instructions

Alter data instructions 1. 0  register CLR [A, B] 2. 0  memory CLR EXT, IND INH N Z V C increment X++ INC [A, B] INC IN [X, Y] 4. decrement X-- DEC [A, B] DEC DE [X, Y] – INH EXT, IND INH – – – INH EXT, IND INH – – – –

Edit instructions - Shifts 1. logical shift right LSR [A, B, D] LSR 2. arithmetic shift right ASR [A, B, D] ASR 3. arithmetic/logical shift left ASL [A, B, D], LSL [A, B, D] ASL, LSL INH EXT, IND INH EXT, IND INH EXT, IND 0 0 n-1 C... 0 n-1 C n-1 C... N Z V C 0

Edit instructions - Rotations 1. rotation right ROL [A, B] ROL 2. rotation left ROR [A, B] ROR INH EXT, IND INH EXT, IND 0 7 C C N Z V C

Logic instructions (1) 1. AND Acc & M  Acc AND [A, B] 2. OR Acc | M  Acc ORA [A, B] 3. XOR Acc  M  Acc EOR [A, B] IMM, DIR, EXT, IND N Z V C IMM, DIR, EXT, IND 0 –

Logic instructions (2) 1. complement X  X COM [A, B] COM 2. bit set M | mask  M BSET 3. bit clear M & mask  M BCLR INH EXT, IND N Z V C DIR, IND – DIR, IND

3. test register TST [A, B] 4. test memory TST 0 INH EXT, IND IMM, DIR, EXT, IND 1. comparison R - M CMP [A, B] CP [D, X, Y] Data test instructions (1) N Z V C INH 2. comparison A – B CBA

0 –IMM, DIR, EXT, IND 1. Bit test Acc & memory BIT [A, B] Data test instructions (2) N Z V C

Control instructions (1) - Branches REL N Z V C – – after comparison register vs. memory unsigned numberssigned numbers BHI higher > BLO lower < BHS higher or same  BLS lower or same  BGT greater than > BLT less than < BGE greater than or equal  BLE less than or equal  BEQ equal = BNE not equal 

Control instructions (2) - Branches after arithmetic operations (testing for overflow) unsigned numberssigned numbers BCS carry set BCC carry clear BVS overflow set BVC overflow clear BPL plus  0 BMI minus < 0 after testing register or memory unconditional BRA always BRN never

Condition code instructions 1. set a flag 1  flag SE [C, V, I] 2. clear a flag 0  flag CL [C, V, I] 3. change all flags A  CC TAP 4. read all flags CC  A TPA

3. test register TST [A, B] 4. test memory TST 0 INH EXT, IND IMM, DIR, EXT, IND 1. comparison R - M CMP [A, B] CP [D, X, Y] Data test instructions (1) N Z V C INH 2. comparison A – B CBA

0 –IMM, DIR, EXT, IND 1. Bit test Acc & memory BIT [A, B] Data test instructions (2) N Z V C

Opcode Map

Interface to External Memory

Write Cycle