32-bit Pipelined RISC Processor Group 1 aka “Go Us” Alice Wang Ann Ho Jason Fong CS m152b TA: Young Cho Lab section 1

General Review of a Pipelined Processor Instruction Memory Register File ALU Data Memory PC Control IF/ID ID/EXEX/MEMMEM/WB

Memory Controller Design Design challenge: 32-bit processor with 16-bit memory interface On every memory access, need to get two words from memory Solution: Clock memory controller twice as fast as rest of processor Results in a memory access on the rising and falling edge of the processor’s clock cycle Data Memory One request16-bit interface Two 16-bit words 32-bit word ? Request Processor Memory 16-bits 32-bits 32-bit

Instruction Format R-type instruction 4 bits remaining 28 bits vary according to instruction type General instruction format opcode rs rt rd unused 3 0 funct 3 0 funct I-type instruction opcode rs rt unused 15 0 imm opcode rs rt unused 15 0 imm16 J-type instruction opcode unused 15 0 imm opcode rs rt rd opcode unused 15 0 imm16

R-type instructionsI-type instructionsJ-type instructions

ALU with Multiplier Our_mult

Multiplier Uses a series of shifts and additions Example: 13 x 11 = x multiplicand multiplier x 1 = HI LO = 1 =  = 143

multiplier (more efficient, but more hardware)

Data Forwarding ID/EXEX/MEMMEM/WB Forward From ALU output Forward From memory output

Hardware NOP Insertion NOP 1 IF/ID PC Adder Hold PC value Insert NOP

Data Forwarding and Stall Insertions: Observed Results Sample program: Bubble-sort 6 numbers Assembler insertion of NOPs Machine code size: 66 words of memory Execution time: ~750 clock cycles Hardware data forwarding and NOP insertion: Machine code size: 35 words of memory Execution time: ~400 clock cycles

Data Forwarding and Stall Insertions: Observed Results Benefits: Savings in memory and execution time Much simpler assembler Drawbacks: Hardware is now more complex Tradeoff between hardware complexity and software complexity Also demonstrates benefits of understanding the underlying architecture when designing an assembler

Conclusion Some problems we encountered: Off by one stage in pipeline Lack of experience with VHDL Order of bits from memory In Conclusion... Knowledge from previous courses Further research Simple RISC processor Pipelining Multiplier Data Forwarding and Hardware NOP’s

References Hennessey and Patterson, Computer Organization and Design (2nd Ed.), 1998, pages Donaldson, John L., “Pipeline Hazards”, Ercegovac, Intro To Digital Systems Institute of Electronics, Information and Communication Engineers. "High Speed and Very Compact Two's Complement Serial/Parallel Multipliers Using Xilinx's FPGA"., Abdelkrim Kamel Oudjida 19 Nov. 2002,

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